Represents the addressing mode used in ARM64 memory access.

Represents an immediate or register-based shift amount.

Represents a parser for 64-bit ARM instructions.

Represents an optional limitation on the barrier operation in ARM64 system instructions.

Represents a condition code used in the A64 ISA, which includes instructions that either set condition flags, test condition codes, or both.

Represents an immediate constant value used in ARM64 instructions.

Represents a register extension with an optional offset.

Represents value extension types used in ARM64 instructions.

Represents an immediate offset or PC-relative label.

Represents an element index in a SIMD vector register.

Represents an ARM64 instruction.

Represents a constant label used in PC-relative instructions.

Represents offset values used in memory addressing.

Represents an ARM64 (AArch64) opcode.

Represents a single operand used in an ARM64 instruction.

Represents a set of operands in an ARM64 instruction.

Represents prefetch operations used for memory hint instructions.

Represents processor state specifiers for ARM64 system instructions.

Provides functions to handle ARM64 registers.

Represents registers for ARMv8 (AArch64).

Represents a factory for accessing various ARM64 register variables.

Represents register-based offset used in ARM64 memory addressing.

Represents a scalar SIMD or FP register in ARM64.

Represents a shift operation with type and amount.

Represents shift types used in ARM64.

Represents a SIMD/FP register used in ARM64 instructions, including scalar and vector forms.

Represents SIMD vector types.

Represents a SIMD vector register with a vector type.

Represents a SIMD vector register with an element index.