|
AddressingMode
|
|
|
Align
|
|
|
Amount
|
|
|
ARM32Instruction
|
The internal representation for an ARM32 instruction used by our
disassembler and lifter.
|
|
ARM32InternalInstruction
|
Basic information for a single ARMv7 instruction obtained after parsing.
|
|
ARM32Parser
|
Parser for 32-bit ARM instructions. Parser will return a platform-agnostic
instruction type (Instruction).
|
|
ARM32RegisterFactory
|
|
|
ARM32TranslationContext
|
Translation context for 32-bit ARM instructions (ARMv7 and ARMv8 AARCH32).
|
|
BarrierOption
|
|
|
Condition
|
|
|
Const
|
|
|
Element
|
|
|
Iflag
|
|
|
IRHelper
|
|
|
Label
|
|
|
OD
|
|
|
Offset
|
|
|
Opcode
|
ARM32 opcodes. This type should be generated using
scripts/genOpcode.fsx from the `ARM32SupportedOpcode.txt` file.
|
|
Operand
|
|
|
OperandParser
|
|
|
OperandParsingHelper
|
|
|
Operands
|
|
|
OprDesc
|
|
|
ParsingHelper
|
|
|
PSRFlag
|
|
|
Qualifier
|
A8.2 Standard assembler syntax fields
|
|
RegExprs
|
|
|
Register (Module)
|
This module exposes several useful functions to handle ARMv8 registers.
|
|
Register (Type)
|
ARMv7, ARMv8 AARCH32 registers.
|
|
Shift
|
|
|
Sign
|
|
|
SIMDDataType
|
A2.6.3 Data types supported by the Advanced SIMD Extension
|
|
SIMDDataTypes
|
|
|
SIMDFPRegister
|
|
|
SIMDOperand
|
|
|
SRType
|
|
B2R2