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AddressingMode
|
|
|
Amount
|
|
|
ARM64Instruction
|
The internal representation for an ARM64 instruction used by our
disassembler and lifter.
|
|
ARM64Parser
|
Parser for 64-bit ARM instructions. Parser will return a platform-agnostic
instruction type (Instruction).
|
|
ARM64RegisterFactory
|
|
|
ARM64TranslationContext
|
Translation context for 64-bit ARM instructions.
|
|
Condition
|
Condition Code. The A64 ISA has some instructions that set condition flags
or test condition codes or both.
|
|
Const
|
|
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ExtendRegisterOffset
|
|
|
ExtendType
|
|
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ImmOffset
|
|
|
Index
|
|
|
InsInfo
|
Basic information for a single ARMv8 instruction obtained after parsing.
|
|
InvalidRegAccessException
|
This is a fatal error that happens when B2R2 tries to access non-existing
register symbol. This exception should not happen in general.
|
|
InvalidTypeException
|
|
|
Label
|
|
|
Offset
|
|
|
Opcode
|
ARMv8 (AArch64) opcodes. This type should be generated using
scripts/genOpcode.fsx from the `ARM64SupportedOpcodes.txt` file.
|
|
Operand
|
|
|
Operands
|
|
|
OptionOpr
|
|
|
PrefetchOperation
|
|
|
Pstate
|
|
|
RegExprs
|
|
|
Register (Module)
|
This module exposes several useful functions to handle ARMv8 registers.
|
|
Register (Type)
|
ARMv8 (AArch64) registers.
|
|
RegisterOffset
|
|
|
RoundMode
|
|
|
Shift
|
|
|
SIMDFPRegister
|
|
|
SIMDFPscalRegister
|
|
|
SIMDVector
|
|
|
SIMDVectorRegister
|
|
|
SIMDVectorRegisterWithIndex
|
SIMD vector register with element index
|
|
SRType
|
|
|
SystemOp
|
|
|
UnallocatedException
|
|
|
UnknownRegException
|
|
B2R2