The internal representation for an ARM64 instruction used by our disassembler and lifter.

Parser for 64-bit ARM instructions. Parser will return a platform-agnostic instruction type (Instruction).

Translation context for 64-bit ARM instructions.

Condition Code. The A64 ISA has some instructions that set condition flags or test condition codes or both.

Basic information for a single ARMv8 instruction obtained after parsing.

This is a fatal error that happens when B2R2 tries to access non-existing register symbol. This exception should not happen in general.

ARMv8 (AArch64) opcodes. This type should be generated using scripts/genOpcode.fsx from the `ARM64SupportedOpcodes.txt` file.

ARMv8 instruction parser.

This module exposes several useful functions to handle ARMv8 registers.

ARMv8 registers. Below is how we encode register as a 20-bit integer.

   19 18 17 16 15        ...        00 (bit position)
   +----------+----------------------+
   | Kind     |  Register ID.        |
   +----------+----------------------+

   # Kind (19 - 16)
   - 0000 : General purpose registers.
   - 0001 : SIMD registers.
   - 0010 : VFP registers.
   - 0011 : Co-processor registers.
   - 0100 : Control flags.
   - 0101 : Control register.

SIMD&FP Register

SIMD vector register

SIMD vector register with element index