Absolute value (vector and scalar form).

Add with carry.

Add with carry and set flags.

Add.

Add returning high, narrow (vector form).

Add returning high, narrow (vector form).

Add pairwise (vector and scalar form).

Add and set flags.

Add (across vector).

Compute address of label at a PC-relative offset.

Compute address of 4KB page at a PC-relative offset.

AES single round decryption.

AES single round encryption.

AES inverse mix columns.

AES mix columns.

Bitwise AND.

Bitwise AND and set flags.

Arithmetic shift right.

Arithmetic shift right variable.

Branch unconditionally.

Branch conditionally (AL).

Branch conditionally (CC).

Branch conditionally (CS).

Branch conditionally (EQ).

Bitfield insert.

Bitfield extract and insert low.

Branch conditionally (GE).

Branch conditionally (GT).

Branch conditionally (HI).

Branch conditionally (HS).

Bitwise bit clear.

Bitwise bit clear and set flags.

Bitwise insert if false (vector form).

Bitwise insert if true (vector form).

Branch with link.

Branch conditionally (LE).

Branch conditionally (LO).

Branch with link to register.

Branch conditionally (LS).

Branch conditionally (LT).

Branch conditionally (MI).

Branch conditionally (NE).

Branch conditionally (NV).

Branch conditionally (PL).

Branch to register.

Breakpoint Instruction.

Bitwise select (vector form).

Branch conditionally (VC).

Branch conditionally (VS).

Compare and branch if nonzero.

Compare and branch if zero.

Conditional compare negative (register or immediate).

Conditional compare (register or immediate).

Conditional increment.

Conditional invert.

Clear exclusive monitor.

Count leading sign bits.

Count leading zero bits.

Compare bitwise equal (vector and scalar form).

Compare signed greater than or equal (vector and scalar form).

Compare signed greater than (vector and scalar form).

Compare unsigned higher (vector and scalar form).

Compare unsigned higher or same (vector and scalar form).

Compare signed less than or equal to zero (vector and scalar form).

Compare signed less than zero (vector and scalar form).

Compare negative.

Compare negative.

Compare bitwise test bits nonzero (vector and scalar form).

Conditional negate.

Population count per byte (vector form).

CRC-32 sum from byte.

CRC-32C sum from byte.

CRC-32C sum from halfword.

CRC-32C sum from word.

CRC-32C sum from doubleword.

CRC-32 sum from halfword.

CRC-32 sum from word.

CRC-32 sum from doubleword.

Conditional select.

Conditional set.

Conditional set mask.

Conditional select increment.

Conditional select inversion.

Conditional select negation.

Data cache maintenance

Debug switch to Exception level 1.

Debug switch to Exception level 2.

Debug switch to Exception level 3.

Data memory barrier.

Debug restore PE state.

Data synchronization barrier.

Duplicate general-purpose register to vector.

Bitwise exclusive OR NOT.

Bitwise exclusive OR.

Exception return using current ELR and SPSR.

Extract vector from a pair of vectors.

Extract register from pair.

Floating-point absolute difference (vector and scalar form).

Floating-point absolute (vector form).

Floating-point absolute compare greater than or equal.

Floating-point absolute compare greater than (vector and scalar form).

Floating-point add (vector form).

Floating-point add pairwise (vector and scalar form).

Floating-point conditional quiet compare.

Floating-point conditional signaling compare.

Floating-point compare equal (vector and scalar form).

Floating-point compare greater than or equal (vector and scalar form).

Floating-point compare greater than (vector and scalar form).

Floating-point compare less than or equal to zero (vector and scalar).

Floating-point compare less than zero (vector and scalar form).

Floating-point quiet compare.

Floating-point signaling compare.

Floating-point scalar conditional select.

Floating-point convert precision (scalar).

FP convert to signed integer, rounding to nearest with ties to away.

FP convert to unsigned integer, rounding to nearest with ties to away.

Floating-point convert to higher precision long (vector form).

Floating-point convert to higher precision long (vector form).

Floating-point convert to signed integer, rounding toward minus infinity.

FP convert to unsigned integer, rounding toward minus infinity.

Floating-point convert to lower precision narrow (vector form).

Floating-point convert to lower precision narrow (vector form).

FP convert to signed integer, rounding to nearest with ties to even.

FP convert to unsigned integer, rounding to nearest with ties to even.

FP convert to signed integer, rounding toward positive infinity.

FP convert to unsigned integer, rounding toward positive infinity.

FP convert to lower precision narrow, rounding to odd (vector and scalar).

FP convert to lower precision narrow, rounding to odd (vector and scalar).

FP convert to signed integer, rounding toward zero (vector and scalar).

FP convert to unsigned integer, rounding toward zero (vector and scalar).

Floating-point divide.

Floating-point scalar fused multiply-add.

Floating-point maximum.

Floating-point maximum number.

Floating-point maximum number pairwise (vector and scalar form).

Floating-point maximum number (across vector).

Floating-point maximum pairwise (vector and scalar form).

Floating-point maximum (across vector).

Floating-point minimum.

Floating-point minimum number.

Floating-point minimum number pairwise (vector and scalar form).

Floating-point minimum number (across vector).

Floating-point minimum pairwise (vector and scalar form).

Floating-point minimum (across vector).

Floating-point fused multiply-add.

Floating-point fused multiply-subtract.

Floating-point move immediate.

Floating-point scalar fused multiply-subtract.

Floating-point multiply.

Floating-point multiply extended.

Floating-point negate.

Floating-point scalar negated fused multiply-add.

Floating-point scalar negated fused multiply-subtract.

Floating-point scalar multiply-negate.

Floating-point reciprocal estimate (vector and scalar form).

Floating-point reciprocal step (vector and scalar form).

Floating-point reciprocal square root (scalar form).

Floating-point round to integral, to nearest with ties to away.

Floating-point round to integral, using current rounding mode.

Floating-point round to integral, toward minus infinity.

Floating-point round to integral, to nearest with ties to even.

Floating-point round to integral, toward positive infinity.

Floating-point round to integral exact, using current rounding mode.

Floating-point round to integral, toward zero.

Floating-point reciprocal square root estimate.

Floating-point reciprocal square root step (vector and scalar form).

Floating-point square root,

Floating-point subtract.

Unallocated hint.

Halt Instruction.

Generate exception targeting Exception level 2.

Insert vector element from general-purpose register.

Instruction synchronization barrier.

Load single 1-element structure to one lane of one register.

Load single 1-element structure and replicate to all lanes of one reg.

Load multiple 2-element structures to two consecutive registers.

Load single 2-element structure and replicate to all lanes of two regs.

Load multiple 3-element structures to three consecutive registers.

Load single 3-element structure and replicate to all lanes of three regs.

Load multiple 4-element structures to four consecutive registers.

Load single 4-element structure and replicate to all lanes of four regs.

Load-Acquire register.

Load-Acquire byte.

Load-Acquire halfword.

Load-Acquire Exclusive pair.

Load-Acquire Exclusive register.

Load-Acquire Exclusive byte.

Load-Acquire Exclusive halfword.

Load Non-temporal Pair.

Load Pair.

Load Pair signed words.

Load register.

Load byte.

Load halfword.

Load signed byte.

Load signed halfword.

Load signed word.

Load unprivileged register.

Load unprivileged byte.

Load unprivileged halfword.

Load unprivileged signed byte.

Load unprivileged signed halfword.

Load unprivileged signed word.

Load register (unscaled offset).

Load byte (unscaled offset).

Load halfword (unscaled offset).

Load signed byte (unscaled offset).

Load signed halfword (unscaled offset).

Load signed word (unscaled offset).

Load Exclusive pair.

Load Exclusive register.

Load Exclusive byte.

Load Exclusive halfword.

Logical shift left.

Logical shift left variable.

Logical shift right.

Logical shift right variable.

Multiply-add.

Multiply-add to accumulator.

Multiply-subtract from accumulator.

Multiply-negate.

Move.

Move immediate.

Move wide with keep.

Move wide with NOT.

Move wide with zero.

Move System register to general-purpose register.

Move general-purpose register to System register.

Multiply-subtract.

Multiply.

Bitwise NOT.

Move inverted immediate.

Negate.

Negate and set flags.

Negate with carry.

Negate with carry and set flags.

No operation.

Bitwise NOT.

Bitwise inclusive OR NOT.

Bitwise inclusive OR.

Polynomial multiply (vector form).

Polynomial multiply long (vector form).

Polynomial multiply long (vector form).

Prefetch memory.

Prefetch memory (unscaled offset).

Rounding add returning high, narrow (vector form).

Rounding add returning high, narrow (vector form).

Reverse bit order.

Return from subroutine.

Reverse bytes in register.

Reverse bytes in halfwords.

Reverses bytes in words.

Reverse elements in 64-bit doublewords (vector form).

Rotate right.

Rotate right variable.

Rounding shift right narrow immediate (vector form).

Rounding shift right narrow immediate (vector form).

Rounding subtract returning high, narrow (vector form).

Rounding subtract returning high, narrow (vector form).

Signed absolute difference and accumulate (vector form).

Signed absolute difference and accumulate long (vector form).

Signed absolute difference and accumulate long (vector form).

Signed absolute difference (vector form).

Signed absolute difference long (vector form).