Represents the addressing mode used in ARM32 memory access.

Represents memory alignment value used in SIMD addressing.

Represents an immediate value used as a shift amount.

Represents a parser for 32-bit ARM instructions.

Represents memory barrier options used in ARM32 DMB and DSB instructions.

Represents the conditional execution behavior of ARM instructions. Most ARM instructions, and most Thumb instructions from ARMv6T2 onwards, can be executed conditionally, based on the values of the APSR condition flags. Before ARMv6T2, the only conditional Thumb instruction was the 16-bit conditional branch instruction.

Represents an immediate constant value in an instruction.

Represents interrupt mask flags in ARM32 architecture.

Represents a parsing mode switch between Thumb and ARM instructions.

Represents an index into a SIMD scalar register element.

Represents an ARM32 instruction.

Represents a constant label used for PC-relative addressing.

Represents ARM32 offset formats used in memory addressing.

Represents an ARM32 opcode.

Represents a single operand used in an ARM32 instruction.

Represents a set of operands in an ARM32 instruction.

Represents flag combinations used in ARM32 PSR (Program Status Register).

Represents execution variant (e.g., widen or narrow).

Provides functions to handle ARM32 registers.

Represents registers for ARMv7, ARMv8 AArch32.

Represents a factory for accessing various ARM32 register variables.

Represents a shift operation applied to a register or immediate value.

Represents ARM32 shift operation types.

Represents the sign used in offset calculations.

Represents a specific SIMD data type (e.g., 8B, 4H, 2S).

Represents a set of SIMD data types.

Represents a SIMD operand made of one or more SIMD/FP registers.

Represents a SIMD/FP register, either vector or scalar with optional element index.