B2R2
Opcode Type
Represents an ARM32 opcode.
Record fields
| Record Field |
Description
|
Add with Carry.
|
|
Add with Carry and updates the flags.
|
|
Add.
|
|
Add and updates the flags.
|
|
Add Wide (12-bit).
|
|
Form PC-relative Address.
|
|
AES single round decryption.
|
|
AES single round encryption.
|
|
AES inverse mix columns.
|
|
AES mix columns.
|
|
Bitwise AND.
|
|
Bitwise AND and updates the flags.
|
|
Arithmetic Shift Right.
|
|
Arithmetic Shift Right and update the flags.
|
|
Branch or Conditional branch.
|
|
Bit Field Clear.
|
|
Bit Field Insert.
|
|
Bitwise Bit Clear.
|
|
Bitwise Bit Clear and updates the flags.
|
|
Breakpoint.
|
|
Branch with Link.
|
|
Branch with Link and Exchange.
|
|
Branch and Exchange.
|
|
Branch and Exchange Jazelle.
|
|
Compare and Branch on Nonzero.
|
|
Compare and Branch on Zero.
|
|
Coprocessor data operations.
|
|
Coprocessor data operations.
|
|
Clear-Exclusive.
|
|
Count Leading Zeros.
|
|
Compare Negative.
|
|
Compare.
|
|
Change Processor State.
|
|
Change Processor State, Interrupt Disasble.
|
|
Change Processor State, Interrupt Enasble.
|
|
CRC-32 sum from byte.
|
|
CRC-32C sum from byte.
|
|
CRC-32C sum from halfword.
|
|
CRC-32C sum from word.
|
|
CRC-32 sum from halfword.
|
|
CRC-32 sum from word.
|
|
Consumption of Speculative Data Barrier.
|
|
Debug hint.
|
|
Debug switch to Exception level 1.
|
|
Debug switch to Exception level 2.
|
|
Debug switch to Exception level 3.
|
|
Data Memory Barrier.
|
|
Data Synchronization Barrier.
|
|
Enter ThumbEE state.
|
|
Bitwise Exclusive OR.
|
|
Bitwise Exclusive OR and update the flags.
|
|
Exception Return.
|
|
Error Synchronization Barrier.
|
|
Loads multiple SIMD&FP registers.
|
|
Loads multiple SIMD&FP registers.
|
|
Stores multiple SIMD&FP registers .
|
|
Stores multiple SIMD&FP registers .
|
|
Halt Instruction.
|
|
Hypervisor Call.
|
|
Instruction Synchronization Barrier.
|
|
If-Then.
|
|
If-Then.
|
|
If-Then.
|
|
If-Then.
|
|
If-Then.
|
|
If-Then.
|
|
If-Then.
|
|
If-Then.
|
|
If-Then.
|
|
If-Then.
|
|
If-Then.
|
|
If-Then.
|
|
If-Then.
|
|
If-Then.
|
|
If-Then.
|
|
Invalid Opcode.
|
|
Load-Acquire Word.
|
|
Load-Acquire Byte.
|
|
Load-Acquire Exclusive Word.
|
|
Load-Acquire Exclusive Byte.
|
|
Load-Acquire Exclusive Double.
|
|
Load-Acquire Exclusive Halfword.
|
|
Load-Acquire Halfword.
|
|
Load Coprocessor.
|
|
Load Coprocessor.
|
|
Load Coprocessor.
|
|
Load Coprocessor.
|
|
Load Multiple.
|
|
Load Multiple. Decrement After.
|
|
Load Multiple. Decrement Before.
|
|
Load Multiple. Increment After.
|
|
Load Multiple. Increment Before.
|
|
Load Register.
|
|
Load Register Byte.
|
|
Load Register Byte Unprivileged.
|
|
Load Register Dual.
|
|
Load Register Exclusive.
|
|
Load Register Exclusive Byte.
|
|
Load Register Exclusive Doubleword.
|
|
Load Register Exclusive Halfword.
|
|
Load Register Halfword.
|
|
Load Register Halfword Unprivileged.
|
|
Load Register Signed Byte.
|
|
Load Register Signed Byte Unprivileged.
|
|
Load Register Signed Halfword.
|
|
Load Register Signed Halfword Unprivileged.
|
|
Load Register Unprivileged.
|
|
Exit ThumbEE state.
|
|
Logical Shift Left.
|
|
Logical Shift Left and OutSide IT block.
|
|
Logical Shift Right.
|
|
Logical Shift Right and OutSide IT block.
|
|
Move to Coprocessor from ARM core register (T1/A1).
|
|
Move to Coprocessor from ARM core register (T2/A2).
|
|
Move to Coprocessor from two ARM core registers (T1/A1).
|
|
Move to Coprocessor from two ARM core registers (T2/A2).
|
|
Multiply Accumulate.
|
|
Multiply Accumulate and update the flags.
|
|
Multiply and Subtract.
|
|
Move.
|
|
Move and update the flags.
|
|
Move Top (16-bit).
|
|
Move (Only encoding T3 or A2 permitted).
|
|
Move to ARM core register from Coprocessor (T1/A1).
|
|
Move to ARM core register from Coprocessor (T2/A2).
|
|
Move to two ARM core registers from Coprocessor (T1/A1).
|
|
Move to two ARM core registers from Coprocessor (T2/A2).
|
|
Move from Banked or Special register.
|
|
Move to Special register, Application level.
|
|
Multiply.
|
|
Multiply and update the flags.
|
|
Bitwise NOT.
|
|
Bitwise NOT and update the flags.
|
|
No Operation.
|
|
Bitwise OR NOT.
|
|
Bitwise OR NOT and update the flags.
|
|
Bitwise OR.
|
|
Bitwise OR and update the flags.
|
|
Pack Halfword (tbform == FALSE).
|
|
Pack Halfword (tbform == TRUE).
|
|
Preload Data.
|
|
Preload Data (W = 1 in Thumb or R = 0 in ARM).
|
|
Preload Instruction.
|
|
Pop Multiple Registers.
|
|
Physical Speculative Store Bypass Barrier.
|
|
Push Multiple Registers.
|
|
Saturating Add.
|
|
Saturating Add 16-bit.
|
|
Saturating Add 8-bit.
|
|
Saturating Add and Subtract with Exchange, 16-bit.
|
|
Saturating Double and Add.
|
|
Saturating Double and Subtract.
|
|
Saturating Subtract and Add with Exchange, 16-bit.
|
|
Saturating Subtract.
|
|
Saturating Subtract 16-bit.
|
|
Saturating Add 8-bit.
|
|
Reverse Bits.
|
|
Byte-Reverse Word.
|
|
Byte-Reverse Packed Halfword.
|
|
Byte-Reverse Signed Halfword.
|
|
Return From Exception.
|
|
Return From Exception. Decrement After.
|
|
Return From Exception. Decrement Before.
|
|
Return From Exception. Increment After.
|
|
Return From Exception. Increment Before.
|
|
Rotate Right.
|
|
Rotate Right and update the flags.
|
|
Rotate Right with Extend.
|
|
Rotate Right with Extend and update the flags.
|
|
Reverse Subtract.
|
|
Reverse Subtract and update the flags.
|
|
Reverse Subtract with Carry.
|
|
Reverse Subtract with Carry and update the flags.
|
|
Add 16-bit.
|
|
Add 8-bit.
|
|
Add and Subtract with Exchange, 16-bit.
|
|
Speculation Barrier.
|
|
Subtract with Carry.
|
|
Subtract with Carry and update the flags.
|
|
Signed Bit Field Extract.
|
|
Signed Divide.
|
|
Select Bytes.
|
|
Set Endianness.
|
|
Set Privileged Access Never.
|
|
Send Event.
|
|
Send Event Local is a hint instruction.
|
|
SHA1 hash update (choose).
|
|
SHA1 fixed rotate.
|
|
SHA1 hash update (majority).
|
|
SHA1 hash update (parity).
|
|
SHA1 schedule update 0.
|
|
SHA1 schedule update 1.
|
|
SHA256 schedule update 0.
|
|
SHA256 hash update (part 2).
|
|
SHA256 schedule update 0.
|
|
SHA256 schedule update 1.
|
|
Halving Add 16-bit.
|
|
Halving Add 8-bit.
|
|
Halving Add and Subtract with Exchange, 16-bit.
|
|
Halving Subtract and Add with Exchange, 16-bit.
|
|
Halving Subtract 16-bit.
|
|
Halving Subtract 8-bit.
|
|
Secure Monitor Call.
|
|
Signed Multiply Accumulate (Halfwords).
|
|
Signed Multiply Accumulate (Halfwords).
|
|
Signed Multiply Accumulate Dual.
|
|
Signed Multiply Accumulate Dual (M = 1).
|
|
Signed Multiply Accumulate Long.
|
|
Signed Multiply Accumulate Long (Halfwords).
|
|
Signed Multiply Accumulate Long (Halfwords).
|
|
Signed Multiply Accumulate Long Dual.
|
|
Signed Multiply Accumulate Long Dual (M = 1).
|
|
Signed Multiply Accumulate Long and update the flags.
|
|
Signed Multiply Accumulate Long.
|
|
Signed Multiply Accumulate Long (Halfwords).
|
|
Signed Multiply Accumulate (Halfwords).
|
|
Signed Multiply Accumulate (Halfwords).
|
|
Signed Multiply Accumulate (Word by halfword).
|
|
Signed Multiply Accumulate.
|
|
Signed Multiply Subtract Dual.
|
|
Signed Multiply Subtract Dual (M = 1).
|
|
Signed Multiply Subtract Long Dual.
|
|
Signed Multiply Subtract Long Dual (M = 1).
|
|
Signed Most Significant Word Multiply Accumulate.
|
|
Signed Most Significant Word Multiply Accumulate (R = 1).
|
|
Signed Most Significant Word Multiply Subtract.
|
|
Signed Most Significant Word Multiply Subtract (R = 1).
|
|
Signed Most Significant Word Multiply.
|
|
Signed Most Significant Word Multiply (R = 1).
|
|
Signed Dual Multiply Add.
|
|
Signed Dual Multiply Add (M = 1).
|
|
Signed Multiply (Halfwords).
|
|
Signed Multiply (Halfwords).
|
|
Signed Multiply Long.
|
|
Signed Multiply Long and update the flags.
|
|
Signed Multiply Long (Halfwords).
|
|
Signed Multiply Long (Halfwords).
|
|
Signed Multiply Accumulate (Word by halfword).
|
|
Signed Multiply Accumulate (Word by halfword).
|
|
Signed Dual Multiply Subtract.
|
|
Signed Dual Multiply Subtract (M = 1).
|
|
Store Return State.
|
|
Store Return State. Decrement After.
|
|
Store Return State. Decrement Before.
|
|
Store Return State. Increment After.
|
|
Store Return State. Increment Before.
|
|
Signed Saturate.
|
|
Signed Saturate, two 16-bit.
|
|
Subtract and Add with Exchange, 16-bit.
|
|
Speculative Store Bypass Barrier.
|
|
Subtract 16-bit.
|
|
Subtract 8-bit.
|
|
Store Coprocessor (T1/A1).
|
|
Store Coprocessor (T2/A2).
|
|
Store Coprocessor (T2/A2) (D == 1).
|
|
Store Coprocessor (T1/A1) (D == 1).
|
|
Store-Release Word.
|
|
Store-Release Byte.
|
|
Store-Release Exclusive Word.
|
|
Store-Release Exclusive Byte.
|
|
Store-Release Exclusive Doubleword.
|
|
Store-Release Exclusive Halfword.
|
|
Store-Release Halfword.
|
|
Store Multiple.
|
|
Store Multiple. Decrement After.
|
|
Store Multiple. Decrement Before.
|
|
Store Multiple. Increment After.
|
|
Store Multiple. Increment After.
|
|
Store Multiple. Increment Before.
|
|
Store Register.
|
|
Store Register Byte.
|
|
Store Register Byte Unprivileged.
|
|
Store Register Dual.
|
|
Store Register Exclusive.
|
|
Store Register Exclusive Byte.
|
|
Store Register Exclusive Doubleword.
|
|
Store Register Exclusive Halfword.
|
|
Store Register Halfword.
|
|
Store Register Halfword Unprivileged.
|
|
Store Register Unprivileged.
|
|
Subtract.
|
|
Subtract and update the flags.
|
|
Subtract Wide.
|
|
Supervisor Call.
|
|
Swap Word.
|
|
Swap Byte.
|
|
Signed Extend and Add Byte.
|
|
Signed Extend and Add Byte 16.
|
|
Signed Extend and Add Halfword.
|
|
Signed Extend Byte.
|
|
Signed Extend Byte 16.
|
|
Signed Extend Halfword.
|
|
Table Branch (byte offsets).
|
|
Table Branch (halfword offsets).
|
|
Test Equivalence.
|
|
Trace Synchronization Barrier.
|
|
Test performs a bitwise AND operation.
|
|
Add 16-bit.
|
|
Add 8-bit.
|
|
Add and Subtract with Exchange, 16-bit.
|
|
Unsigned Bit Field Extract.
|
|
Permanently UNDEFINED.
|
|
Unsigned Divide.
|
|
Halving Add 16-bit.
|
|
Halving Add 8-bit.
|
|
Halving Add and Subtract with Exchange, 16-bit.
|
|
Halving Subtract and Add with Exchange, 16-bit.
|
|
Halving Subtract 16-bit.
|
|
Halving Add 8-bit.
|
|
Unsigned Multiply Accumulate Accumulate Long.
|
|
Unsigned Multiply Accumulate Long.
|
|
Unsigned Multiply Accumulate Long and update the flags.
|
|
Unsigned Multiply Long.
|
|
Unsigned Multiply Long and update the flags.
|
|
Saturating Add 16-bit.
|
|
Saturating Add 8-bit.
|
|
Saturating Add and Subtract with Exchange, 16-bit.
|
|
Saturating Subtract and Add with Exchange, 16-bit.
|
|
Saturating Subtract 16-bit.
|
|
Saturating Subtract 8-bit.
|
|
Unsigned Sum of Absolute Differences.
|
|
Unsigned Sum of Absolute Differences, Accumulate.
|
|
Unsigned Saturate.
|
|
Unsigned Saturate, two 16-bit.
|
|
Subtract and Add with Exchange, 16-bit.
|
|
Subtract 16-bit.
|
|
Subtract 8-bit.
|
|
Unsigned Extend and Add Byte.
|
|
Unsigned Extend and Add Byte 16.
|
|
Unsigned Extend and Add Halfword.
|
|
Unsigned Extend Byte.
|
|
Unsigned Extend Byte 16.
|
|
Unsigned Extend Halfword.
|
|
Vector Absolute Difference and Accumulate.
|
|
Vector Absolute Difference and Accumulate (T2/A2).
|
|
Vector Absolute Difference.
|
|
Vector Absolute Difference (T2/A2).
|
|
Vector Absolute.
|
|
Vector Absolute Compare Greater or Less Than (or Equal).
|
|
Vector Absolute Compare Greater or Less Than (or Equal).
|
|
Vector Absolute Compare Greater or Less Than (or Equal).
|
|
Vector Absolute Compare Greater or Less Than (or Equal).
|
|
Vector Add.
|
|
Vector Add and Narrow, returning High Half.
|
|
Vector Add Long.
|
|
Vector Add Wide.
|
|
Vector Bitwise AND.
|
|
Vector Bitwise Bit Clear, AND complement.
|
|
Vector Bitwise Select. Bitwise Insert if False, encoded as op = 0b11.
|
|
Vector Bitwise Select. Bitwise Insert if True, encoded as op = 0b10.
|
|
Vector Bitwise Select. Bitwise Select, encoded as op = 0b01.
|
|
Vector Complex Add.
|
|
Vector Compare Equal.
|
|
Vector Compare Greater Than or Equal.
|
|
Vector Compare Greater Than.
|
|
Vector Compare Less Than or Equal to Zero.
|
|
Vector Count Leading Sign Bits.
|
|
Vector Compare Less Than Zero.
|
|
Vector Count Leading Zeros.
|
|
Vector Complex Multiply Accumulate.
|
|
Vector Compare. (Encoded as E = 0).
|
|
Vector Compare. (Encoded as E = 1).
|
|
Vector Count.
|
|
Vector Convert.
|
|
Convert floating-point to integer with Round to Nearest with Ties to Away.
|
|
Convert between half-precision and single-precision.
|
|
Convert floating-point to integer with Round towards Minus Infinity.
|
|
Convert floating-point to integer with Round to Nearest.
|
|
Convert floating-point to integer with Round towards Plus Infinity.
|
|
Vector Convert floating-point to integer.
|
|
Convert between half-precision and single-precision.
|
|
Vector Divide.
|
|
BFloat16 floating-point (BF16) dot product (vector).
|
|
Vector Duplicate.
|
|
Vector Bitwise Exclusive OR.
|
|
Vector Extract.
|
|
Vector Fused Multiply Accumulate.
|
|
BFloat16 floating-point widening multiply-add.
|
|
Vector Floating-point Multiply-Add Long to accumulator.
|
|
BFloat16 floating-point widening multiply-add.
|
|
Vector Fused Multiply Subtract.
|
|
Vector Floating-Point Multiply-Subtract Long.
|
|
Vector Fused Negate Multiply Accumulate.
|
|
Vector Fused Negate Multiply Subtract.
|
|
Vector Halving Add.
|
|
Vector Halving Subtract.
|
|
Vector move Insertion.
|
|
FP Javascript convert to signed fixed-point, rounding toward zero.
|
|
Vector Load. (multiple single elements).
|
|
Vector Load. (multiple 2-element structures).
|
|
Vector Load. (multiple 3-element structures).
|
|
Vector Load. (multiple 4-element structures).
|
|
Vector Load Multiple.
|
|
Vector Load Multiple. Decrement Before.
|
|
Vector Load Multiple. Increment After.
|
|
Vector Load Register.
|
|
Vector Maximum.
|
|
Floating-point Maximum Number.
|
|
Vector Minimum.
|
|
Floating-point Minimum Number.
|
|
Vector Multiply Accumulate.
|
|
Vector Multiply Accumulate (T2/A2).
|
|
Vector Multiply Subtract.
|
|
Vector Multiply Subtract (T2/A2).
|
|
BFloat16 floating-point matrix multiply-accumulate.
|
|
Vector Move.
|
|
Vector Move Long.
|
|
Vector Move and Narrow.
|
|
Vector Move extraction.
|
|
Move to ARM core register from Floating-point Special register.
|
|
Move to Floating-point Special register from ARM core register.
|
|
Vector Multiply.
|
|
Vector Multiply Long.
|
|
Vector Bitwise NOT.
|
|
Vector Negate.
|
|
Vector Negate Multiply Accumulate or Subtract.
|
|
Vector Negate Multiply Accumulate or Subtract.
|
|
Vector Negate Multiply Accumulate or Subtract.
|
|
Vector Bitwise OR NOT.
|
|
Vector Bitwise OR, if source registers differ.
|
|
Vector Pairwise Add and Accumulate Long.
|
|
Vector Pairwise Add.
|
|
Vector Pairwise Add Long.
|
|
Vector Pairwise Maximum.
|
|
Vector Pairwise Minimum.
|
|
Vector Pop Registers.
|
|
Vector Push Registers.
|
|
Vector Saturating Absolute.
|
|
Vector Saturating Add.
|
|
Vector Saturating Doubling Multiply Accumulate Long.
|
|
Vector Saturating Doubling Multiply Subtract Long.
|
|
Vector Saturating Doubling Multiply returning High Half.
|
|
Vector Saturating Doubling Multiply Long.
|
|
Vector Saturating Move and Unsigned Narrow (op <> 0b01).
|
|
Vector Saturating Move and Unsigned Narrow (op = 0b01).
|
|
Vector Saturating Negate.
|
|
Vector Saturating Rounding Doubling Mul Accumulate Returning High Half.
|
|
Vector Saturating Rounding Doubling Multiply Subtract Returning High Half.
|
|
Vector Saturating Rounding Doubling Multiply returning High Half.
|
|
Vector Saturating Rounding Shift Left.
|
|
Vector Saturating Shift Right, Rounded Unsigned Narrow.
|
|
Vector Saturating Shift Right, Rounded Unsigned Narrow.
|
|
Vector Saturating Shift Left.
|
|
Vector Saturating Shift Left.
|
|
Vector Saturating Shift Right, Narrow.
|
|
Vector Saturating Shift Right, Narrow.
|
|
Vector Saturating Subtract.
|
|
Vector Rounding Add and Narrow, returning High Half.
|
|
Vector Reciprocal Estimate.
|
|
Vector Reciprocal Step.
|
|
Vector Reverse in halfwords.
|
|
Vector Reverse in words.
|
|
Vector Reverse in doublewords.
|
|
Vector Rounding Halving Add.
|
|
Vector Round floating-point to integer towards Nearest with Ties to Away.
|
|
Vector Round floating-point to integer towards Minus Infinity.
|
|
Vector Round floating-point to integer to Nearest.
|
|
Vector Round floating-point to integer towards Plus Infinity.
|
|
Vector Round floating-point to integer rounds.
|
|
Vector round floating-point to integer to nearest signaling inexactness.
|
|
Vector round floating-point to integer towards Zero.
|
|
Vector Rounding Shift Left.
|
|
Vector Rounding Shift Right.
|
|
Vector Rounding Shift Right Narrow.
|
|
Vector Reciprocal Square Root Estimate.
|
|
Vector Reciprocal Square Root Step.
|
|
Vector Rounding Shift Right and Accumulate.
|
|
Vector Rounding Subtract and Narrow, returning High Half.
|
|
Dot Product vector form with signed integers.
|
|
Floating-point conditional select.
|
|
Floating-point conditional select.
|
|
Floating-point conditional select.
|
|
Floating-point conditional select.
|
|
Vector Shift Left.
|
|
Vector Shift Left Long.
|
|
Vector Shift Right.
|
|
Vector Shift Right Narrow.
|
|
Vector Shift Left and Insert.
|
|
The widening integer matrix multiply-accumulate instruction.
|
|
Vector Square Root.
|
|
Vector Shift Right and Accumulate.
|
|
Vector Shift Right and Insert.
|
|
Vector Store. (multiple single elements).
|
|
Vector Store. (multiple 2-element structures).
|
|
Vector Store. (multiple 3-element structures).
|
|
Vector Store. (multiple 4-element structures).
|
|
Vector Store Multiple.
|
|
Vector Store Multiple. Decrement Before.
|
|
Vector Store Multiple. Increment After.
|
|
Vector Store Register.
|
|
Vector Subtract.
|
|
Vector Subtract and Narrow, returning High Half.
|
|
Vector Subtract Long.
|
|
Vector Subtract Wide.
|
|
Dot Product index form with signed and unsigned integers.
|
|
Vector Swap.
|
|
Vector Table Lookup.
|
|
Vector Table Extension.
|
|
Vector Transpose.
|
|
Vector Test Bits.
|
|
Dot Product index form with unsigned integers.
|
|
Widening 8-bit unsigned int matrix multiply-accumulate into 2x2 matrix.
|
|
Dot Product index form with unsigned and signed integers.
|
|
Widening 8-bit mixed sign int matrix multiply-accumulate into 2x2 matrix.
|
|
Vector Unzip.
|
|
Vector Zip.
|
|
Wait For Event hint.
|
|
Wait For Interrupt hint.
|
|
Yield hint.
|