Opcode Type
Intel opcodes. This type should be generated using
scripts/genOpcode.fsx from the `IntelSupportedOpcodes.txt` file.
Record fields
| Record Field | Description |
ASCII Adjust After Addition.
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ASCII Adjust AX Before Division.
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ASCII Adjust AX After Multiply.
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ASCII Adjust AL After Subtraction.
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Add with Carry.
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Unsigned integer add with carry.
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Add.
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Add Packed Double-Precision Floating-Point Values.
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Add Packed Single-Precision Floating-Point Values.
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Add Scalar Double-Precision Floating-Point Values.
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Add Scalar Single-Precision Floating-Point Values.
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Packed Double-FP Add/Subtract.
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Packed Single-FP Add/Subtract.
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Unsigned integer add with overflow.
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Perform an AES decryption round using an 128-bit state and a round key.
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|
Perform Last Round of an AES Decryption Flow.
|
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Perform an AES encryption round using an 128-bit state and a round key.
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Perform Last Round of an AES Encryption Flow.
|
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Perform an inverse mix column transformation primitive.
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Assist the creation of round keys with a key expansion schedule.
|
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Logical AND.
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Bitwise AND of first source with inverted 2nd source operands.
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Bitwise Logical AND of Packed Double-Precision Floating-Point Values.
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Bitwise Logical AND of Packed Single-Precision Floating-Point Values.
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Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values.
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Bitwise Logical AND NOT of Packed Single-Precision Floating-Point Values.
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|
Adjust RPL Field of Segment Selector.
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|
Contiguous bitwise extract.
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|
Blend Packed Double Precision Floating-Point Values.
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Blend Packed Single Precision Floating-Point Values.
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Variable Blend Packed Double Precision Floating-Point Values.
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Variable Blend Packed Single Precision Floating-Point Values.
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Extract lowest set bit.
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Set all lower bits below first set bit to 1.
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Reset lowest set bit.
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Check the address of a memory reference against a LowerBound.
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Check Upper Bound.
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Check Upper Bound.
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|
Load Extended Bounds Using Address Translation.
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Create a LowerBound and a UpperBound in a register.
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Move Bounds.
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Store bounds using address translation.
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Check Array Index Against Bounds.
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Bit Scan Forward.
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Bit Scan Reverse.
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Byte Swap.
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Bit Test.
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Bit Test and Complement.
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Bit Test and Reset.
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Bit Test and Set.
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Zero high bits starting from specified bit position.
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|
Far call.
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Near call.
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|
Convert Byte to Word.
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Convert Doubleword to Quadword.
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Convert Doubleword to Quadword.
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Clear AC Flag in EFLAGS Register.
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Clear Carry Flag.
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|
Clear Direction Flag.
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|
Flush Cache Line.
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|
Flush Cache Line Optimized.
|
|
Clear Interrupt Flag.
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Clear busy bit in a supervisor shadow stack token.
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|
Clear Task-Switched Flag in CR0.
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|
Complement Carry Flag.
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|
Conditional Move (Move if above (CF = 0 and ZF = 0)).
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Conditional Move (Move if above or equal (CF = 0)).
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Conditional Move (Move if below (CF = 1)).
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Conditional Move (Move if below or equal (CF = 1 or ZF = 1)).
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|
Conditional move if carry.
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Conditional Move (Move if greater (ZF = 0 and SF = OF)).
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Conditional Move (Move if greater or equal (SF = OF)).
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Conditional Move (Move if less (SF <> OF)).
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Conditional Move (Move if less or equal (ZF = 1 or SF <> OF)).
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|
Conditional move if not carry.
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Conditional Move (Move if not overflow (OF = 0)).
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Conditional Move (Move if not parity (PF = 0)).
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|
Conditional Move (Move if not sign (SF = 0)).
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|
Conditional Move (Move if not zero (ZF = 0)).
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|
Conditional Move (Move if overflow (OF = 1)).
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|
Conditional Move (Move if parity (PF = 1)).
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|
Conditional Move (Move if sign (SF = 1)).
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|
Conditional Move (Move if zero (ZF = 1)).
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|
|
Compare Two Operands.
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|
Compare packed double-precision floating-point values.
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|
Compare packed single-precision floating-point values.
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|
Compare String Operands (byte).
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Compare String Operands (dword) or Compare scalar dbl-precision FP values.
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Compare String Operands (quadword).
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Compare scalar single-precision floating-point values.
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Compare String Operands (word).
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Compare and Exchange.
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Compare and Exchange Bytes.
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Compare and Exchange Bytes.
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Compare Scalar Ordered Double-Precision FP Values and Set EFLAGS.
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Compare Scalar Ordered Single-Precision FP Values and Set EFLAGS.
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CPU Identification.
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Convert Quadword to Octaword.
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Accumulate CRC32 Value.
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Convert Packed Dword Integers to Packed Double-Precision FP Values.
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Convert Packed Dword Integers to Packed Single-Precision FP Values.
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Convert Packed Double-Precision FP Values to Packed Dword Integers.
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Convert Packed Double-Precision FP Values to Packed Dword Integers.
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|
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Convert Packed Double-Precision FP Values to Packed Single-Precision FP.
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|
Convert Packed Dword Integers to Packed Double-Precision FP Values.
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Convert Packed Dword Integers to Packed Single-Precision FP Values.
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Convert Packed Single-Precision FP Values to Packed Dword Integers.
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|
Convert Packed Single-Precision FP Values to Packed Double-Precision FP.
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|
|
Convert Packed Single-Precision FP Values to Packed Dword Integers.
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|
|
Convert Scalar Double-Precision FP Value to Integer.
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|
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Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP.
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|
Convert Dword Integer to Scalar Double-Precision FP Value.
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|
|
Convert Dword Integer to Scalar Single-Precision FP Value.
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Convert Scalar Single-Precision FP Value to Scalar Double-Precision FP.
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Convert Scalar Single-Precision FP Value to Dword Integer.
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|
Convert with Truncation Packed Double-Precision FP Values to Packed Dword.
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Convert with Truncation Packed Double-Precision FP Values to Packed Dword.
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Convert with Truncation Packed Single-Precision FP Values to Packed Dword.
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Convert with Truncation Packed Single-Precision FP Values to Packed Dword.
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Convert with Truncation Scalar Double-Precision FP Value to Signed.
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Convert with Truncation Scalar Single-Precision FP Value to Dword Integer.
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Convert Word to Doubleword.
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Convert Word to Doubleword.
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Decimal Adjust AL after Addition.
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Decimal Adjust AL after Subtraction.
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Decrement by 1.
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Unsigned Divide.
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Divide Packed Double-Precision Floating-Point Values.
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Divide Packed Single-Precision Floating-Point Values.
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|
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Divide Scalar Double-Precision Floating-Point Values.
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|
Divide Scalar Single-Precision Floating-Point Values.
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|
|
Perform double-precision dot product for up to 2 elements and broadcast.
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|
Perform single-precision dot products for up to 4 elements and broadcast.
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|
Empty MMX Technology State.
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|
Execute an Enclave System Function of Specified Leaf Number.
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Execute an Enclave User Function of Specified Leaf Number.
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|
Terminate an Indirect Branch in 32-bit and Compatibility Mode.
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|
Terminate an Indirect Branch in 64-bit Mode.
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Make Stack Frame for Procedure Parameters.
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Extract Packed Floating-Point Values.
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Compute 2x-1.
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Absolute Value.
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Add.
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Add and pop the register stack.
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Load Binary Coded Decimal.
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Store BCD Integer and Pop.
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Change Sign.
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Clear Exceptions.
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Floating-Point Conditional Move (if below (CF = 1)).
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Floating-Point Conditional Move (if below or equal (CF = 1 or ZF = 1)).
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|
Floating-Point Conditional Move (if equal (ZF = 1)).
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|
Floating-Point Conditional Move (if not below (CF = 0)).
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|
FP Conditional Move (if not below or equal (CF = 0 and ZF = 0)).
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|
|
Floating-Point Conditional Move (if not equal (ZF = 0)).
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|
Floating-Point Conditional Move (if not unordered (PF = 0)).
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|
Floating-Point Conditional Move (if unordered (PF = 1)).
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|
Compare Floating Point Values.
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Compare Floating Point Values and Set EFLAGS.
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Compare Floating Point Values and Set EFLAGS.
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Compare Floating Point Values and pop register stack.
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|
Compare Floating Point Values and pop register stack twice.
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Cosine.
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Decrement Stack-Top Pointer.
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Divide.
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Divide and pop the register stack.
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Reverse Divide.
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Reverse Divide and pop the register stack.
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Free Floating-Point Register.
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Add.
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Compare Integer.
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Compare Integer and pop the register stack.
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Divide.
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Reverse Divide.
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Load Integer.
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Multiply.
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Increment Stack-Top Pointer.
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Initialize Floating-Point Unit.
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Store Integer.
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Store Integer and pop the register stack.
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Store Integer with Truncation.
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Subtract.
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Reverse Subtract.
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|
Load Floating Point Value.
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|
Load Constant (Push +1.0 onto the FPU register stack).
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Load x87 FPU Control Word.
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|
Load x87 FPU Environment.
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|
Load Constant (Push log2e onto the FPU register stack).
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|
Load Constant (Push log210 onto the FPU register stack).
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|
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Load Constant (Push log102 onto the FPU register stack).
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|
|
Load Constant (Push loge2 onto the FPU register stack).
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|
|
Load Constant (Push Pi onto the FPU register stack).
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Load Constant (Push +0.0 onto the FPU register stack).
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Multiply.
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Multiply and pop the register stack.
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|
Clear floating-point exception flags without checking for error conditions.
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Initialize FPU without checking error conditions.
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No Operation.
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Save FPU state without checking error conditions.
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Store x87 FPU Control Word.
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Store FPU environment without checking error conditions.
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Store FPU status word without checking error conditions.
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Partial Arctangent.
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Partial Remainder.
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Partial Remainder.
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Partial Tangent.
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Round to Integer.
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Restore x87 FPU State.
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Store x87 FPU State.
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Scale.
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Sine.
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Sine and Cosine.
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Square Root.
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Store Floating Point Value.
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Store FPU control word after checking error conditions.
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Store x87 FPU Environment.
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Store Floating Point Value.
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Store x87 FPU Status Word.
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Subtract.
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Subtract and pop register stack.
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Reverse Subtract.
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Reverse Subtract and pop register stack.
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TEST.
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Unordered Compare Floating Point Values.
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Compare Floating Point Values and Set EFLAGS.
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Compare Floating Point Values and Set EFLAGS and pop register stack.
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Unordered Compare Floating Point Values.
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Unordered Compare Floating Point Values.
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Wait for FPU.
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Examine ModR/M.
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Exchange Register Contents.
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Restore x87 FPU, MMX, XMM, and MXCSR State.
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Restore x87 FPU, MMX, XMM, and MXCSR State.
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Save x87 FPU, MMX Technology, and SSE State.
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Save x87 FPU, MMX Technology, and SSE State.
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Extract Exponent and Significand.
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compute y * log2x.
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compute y * log2(x+1).
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GETSEC.
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Galois Field Affine Transformation Inverse.
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Galois Field Affine Transformation.
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Galois Field Multiply Bytes.
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Packed Double-FP Horizontal Add.
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Packed Single-FP Horizontal Add.
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Halt.
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Packed Double-FP Horizontal Subtract.
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Packed Single-FP Horizontal Subtract.
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Signed Divide.
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Signed Multiply.
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Input from Port.
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Increment by 1.
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Increment the shadow stack pointer (SSP).
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Increment the shadow stack pointer (SSP).
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Input from Port to String.
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Input from Port to String (byte).
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Input from Port to String (doubleword).
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Insert Scalar Single-Precision Floating-Point Value.
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Input from Port to String (word).
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Call to Interrupt (Interrupt vector specified by immediate byte).
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Call to Interrupt (Interrupt 3-trap to debugger).
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Call to Interrupt (InteInterrupt 4-if overflow flag is 1).
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Invalidate Internal Caches.
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Invalidate Translations Derived from EPT.
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Invalidate TLB Entries.
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Invalidate Process-Context Identifier.
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Invalidate Translations Based on VPID.
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Return from interrupt.
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Interrupt return (32-bit operand size).
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Interrupt return (64-bit operand size).
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Interrupt return (16-bit operand size).
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Invalid Opcode.
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Jump if Condition Is Met (Jump near if not below, CF = 0).
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Jump if Condition Is Met (Jump short if below, CF = 1).
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Jump if Condition Is Met (Jump short if CX register is 0).
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Jump if Condition Is Met (Jump short if ECX register is 0).
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Jump if Condition Is Met (Jump near if not less, SF = OF).
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Far jmp.
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Near jmp.
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Jump if Condition Is Met (Jump short if below or equal, CF = 1 or ZF).
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Jump if Condition Is Met (Jump short if above, CF = 0 and ZF = 0).
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Jump if Cond Is Met (Jump short if less or equal, ZF = 1 or SF <> OF).
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Jump if Condition Is Met (Jump short if less, SF <> OF).
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Jump if Condition Is Met (Jump short if greater, ZF = 0 and SF = OF).
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Jump if Condition Is Met (Jump near if not overflow, OF = 0).
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Jump if Condition Is Met (Jump near if not sign, SF = 0).
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|
Jump if Condition Is Met (Jump near if not zero, ZF = 0).
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|
Jump if Condition Is Met (Jump near if overflow, OF = 1).
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Jump if Condition Is Met (Jump near if parity, PF = 1).
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Jump if Condition Is Met (Jump near if not parity, PF = 0).
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Jump if Condition Is Met (Jump short if RCX register is 0).
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Jump if Condition Is Met (Jump short if sign, SF = 1).
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Jump if Condition Is Met (Jump short if zero, ZF = 1).
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Add two 8-bit opmasks.
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Add two 32-bit opmasks.
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Add two 64-bit opmasks.
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Add two 16-bit opmasks.
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Logical AND two 8-bit opmasks.
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Logical AND two 32-bit opmasks.
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Logical AND NOT two 8-bit opmasks.
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Logical AND NOT two 32-bit opmasks.
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Logical AND NOT two 64-bit opmasks.
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Logical AND NOT two 16-bit opmasks.
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Logical AND two 64-bit opmasks.
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Logical AND two 16-bit opmasks.
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Move from or move to opmask register of 8-bit data.
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Move from or move to opmask register of 32-bit data.
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Move from or move to opmask register of 64-bit data.
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Move from or move to opmask register of 16-bit data.
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Bitwise NOT of two 8-bit opmasks.
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Bitwise NOT of two 32-bit opmasks.
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Bitwise NOT of two 64-bit opmasks.
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Bitwise NOT of two 16-bit opmasks.
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|
Logical OR two 8-bit opmasks.
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|
Logical OR two 32-bit opmasks.
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|
Logical OR two 64-bit opmasks.
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|
|
Update EFLAGS according to the result of bitwise OR of two 8-bit opmasks.
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|
Update EFLAGS according to the result of bitwise OR of two 32-bit opmasks.
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|
Update EFLAGS according to the result of bitwise OR of two 64-bit opmasks.
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|
Update EFLAGS according to the result of bitwise OR of two 16-bit opmasks.
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|
Logical OR two 16-bit opmasks.
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Shift left 8-bitopmask by specified count.
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Shift left 32-bitopmask by specified count.
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Shift left 64-bitopmask by specified count.
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Shift left 16-bitopmask by specified count.
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Shift right 8-bit opmask by specified count.
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Shift right 32-bit opmask by specified count.
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Shift right 64-bit opmask by specified count.
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Shift right 16-bit opmask by specified count.
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|
Update EFLAGS according to result of bitwise TEST of two 8-bit opmasks.
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|
Update EFLAGS according to result of bitwise TEST of two 32-bit opmasks.
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|
Update EFLAGS according to result of bitwise TEST of two 64-bit opmasks.
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|
|
Update EFLAGS according to result of bitwise TEST of two 16-bit opmasks.
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|
|
Unpack and interleave two 8-bit opmasks into 16-bit mask.
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|
|
Unpack and interleave two 32-bit opmasks into 64-bit mask.
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|
Unpack and interleave two 16-bit opmasks into 32-bit mask.
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|
Bitwise logical XNOR of two 8-bit opmasks.
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Bitwise logical XNOR of two 32-bit opmasks.
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Bitwise logical XNOR of two 64-bit opmasks.
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|
Bitwise logical XNOR of two 16-bit opmasks.
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|
Logical XOR of two 8-bit opmasks.
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|
Logical XOR of two 32-bit opmasks.
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|
Logical XOR of two 64-bit opmasks.
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|
Logical XOR of two 16-bit opmasks.
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|
Load Status Flags into AH Register.
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|
Load Access Rights Byte.
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|
Load Unaligned Integer 128 Bits.
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|
Load MXCSR Register.
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|
Load Far Pointer (DS).
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|
Load Effective Address.
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|
High Level Procedure Exit.
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Load Far Pointer (ES).
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|
Load Fence.
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|
Load Far Pointer (FS).
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|
Load GlobalDescriptor Table Register.
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|
Load Far Pointer (GS).
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|
Load Interrupt Descriptor Table Register.
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|
Load Local Descriptor Table Register.
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|
Load Machine Status Word.
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|
Assert LOCK# Signal Prefix.
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|
Load String (byte).
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|
Load String (doubleword).
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|
Load String (quadword).
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|
Load String (word).
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|
|
Loop According to ECX Counter (count <> 0).
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|
Loop According to ECX Counter (count <> 0 and ZF = 1).
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|
|
Loop According to ECX Counter (count <> 0 and ZF = 0).
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|
|
Load Segment Limit.
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|
|
Load Far Pointer (SS).
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|
|
Load Task Register.
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|
|
the Number of Leading Zero Bits.
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|
|
Store Selected Bytes of Double Quadword.
|
|
Store Selected Bytes of Quadword.
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|
|
Return Maximum Packed Double-Precision Floating-Point Values.
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|
Return Maximum Packed Single-Precision Floating-Point Values.
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|
|
Return Maximum Scalar Double-Precision Floating-Point Values.
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|
|
Return Maximum Scalar Single-Precision Floating-Point Values.
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|
|
Memory Fence.
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|
|
Return Minimum Packed Double-Precision Floating-Point Values.
|
|
|
Return Minimum Packed Single-Precision Floating-Point Values.
|
|
|
Return Minimum Scalar Double-Precision Floating-Point Values.
|
|
|
Return Minimum Scalar Single-Precision Floating-Point Values.
|
|
|
Set Up Monitor Address.
|
|
|
MOV.
|
|
|
Move Aligned Packed Double-Precision Floating-Point Values.
|
|
|
Move Aligned Packed Single-Precision Floating-Point Values.
|
|
|
Move Data After Swapping Bytes.
|
|
|
Move Doubleword.
|
|
|
Move One Double-FP and Duplicate.
|
|
|
Move Quadword from XMM to MMX Technology Register.
|
|
|
Move Aligned Double Quadword.
|
|
|
Move Unaligned Double Quadword.
|
|
|
Move Packed Single-Precision Floating-Point Values High to Low.
|
|
|
Move High Packed Double-Precision Floating-Point Value.
|
|
|
Move High Packed Single-Precision Floating-Point Values.
|
|
|
Move Packed Single-Precision Floating-Point Values Low to High.
|
|
|
Move Low Packed Double-Precision Floating-Point Value.
|
|
|
Move Low Packed Single-Precision Floating-Point Values.
|
|
|
Extract Packed Double-Precision Floating-Point Sign Mask.
|
|
|
Extract Packed Single-Precision Floating-Point Sign Mask.
|
|
|
Load Double Quadword Non-Temporal Aligned Hint.
|
|
|
Load Double Quadword Non-Temporal Aligned Hint.
|
|
|
Store Doubleword Using Non-Temporal Hint.
|
|
|
Store Packed Double-Precision FP Values Using Non-Temporal Hint.
|
|
|
Store Packed Single-Precision FP Values Using Non-Temporal Hint.
|
|
|
Store of Quadword Using Non-Temporal Hint.
|
|
|
Move Quadword.
|
|
|
Move Quadword from MMX Technology to XMM Register.
|
|
|
Move Data from String to String (byte).
|
|
|
Move Data from String to String (doubleword).
|
|
|
Move Packed Single-FP High and Duplicate.
|
|
|
Move Packed Single-FP Low and Duplicate.
|
|
|
Move Data from String to String (quadword).
|
|
|
Move Scalar Single-Precision Floating-Point Values.
|
|
|
Move Data from String to String (word).
|
|
|
Move with Sign-Extension.
|
|
|
Move with Sign-Extension (doubleword to quadword).
|
|
|
Move Unaligned Packed Double-Precision Floating-Point Values.
|
|
|
Move Unaligned Packed Single-Precision Floating-Point Values.
|
|
|
Move with Zero-Extend.
|
|
|
Compute Multiple Packed Sums of Absolute Difference.
|
|
|
Unsigned Multiply.
|
|
|
Multiply Packed Double-Precision Floating-Point Values.
|
|
|
Multiply Packed Single-Precision Floating-Point Values.
|
|
|
Multiply Scalar Double-Precision Floating-Point Values.
|
|
|
Multiply Scalar Single-Precision Floating-Point Values.
|
|
|
Unsigned multiply without affecting arithmetic flags.
|
|
|
Monitor Wait.
|
|
|
Two's Complement Negation.
|
|
|
No Operation.
|
|
|
One's Complement Negation.
|
|
|
Logical Inclusive OR.
|
|
|
Bitwise Logical OR of Double-Precision Floating-Point Values.
|
|
|
Bitwise Logical OR of Single-Precision Floating-Point Values.
|
|
|
Output to Port.
|
|
|
Output String to Port.
|
|
|
Output String to Port (byte).
|
|
|
Output String to Port (doubleword).
|
|
|
Output String to Port (word).
|
|
|
Computes the absolute value of each signed byte data element.
|
|
|
Computes the absolute value of each signed 32-bit data element.
|
|
|
Computes the absolute value of each signed 16-bit data element.
|
|
|
Pack with Signed Saturation.
|
|
|
Pack with Signed Saturation.
|
|
|
Pack with Unsigned Saturation.
|
|
|
Pack with Unsigned Saturation.
|
|
|
Add Packed byte Integers.
|
|
|
Add Packed Doubleword Integers.
|
|
|
Add Packed Quadword Integers.
|
|
|
Add Packed Signed Integers with Signed Saturation (byte).
|
|
|
Add Packed Signed Integers with Signed Saturation (word).
|
|
|
Add Packed Unsigned Integers with Unsigned Saturation (byte).
|
|
|
Add Packed Unsigned Integers with Unsigned Saturation (word).
|
|
|
Add Packed word Integers.
|
|
|
Packed Align Right.
|
|
|
Logical AND.
|
|
|
Logical AND NOT.
|
|
|
Spin Loop Hint.
|
|
|
Average Packed Integers (byte).
|
|
|
Average Packed Integers (word).
|
|
|
Variable Blend Packed Bytes.
|
|
|
Blend Packed Words.
|
|
|
Perform carryless multiplication of two 64-bit numbers.
|
|
|
Compare Packed Data for Equal (byte).
|
|
|
Compare Packed Data for Equal (doubleword).
|
|
|
Compare Packed Data for Equal (quadword).
|
|
|
Compare packed words for equal.
|
|
|
Packed Compare Explicit Length Strings, Return Index.
|
|
|
Packed Compare Explicit Length Strings, Return Mask.
|
|
|
Compare Packed Signed Integers for Greater Than (byte).
|
|
|
Compare Packed Signed Integers for Greater Than (doubleword).
|
|
|
Performs logical compare of greater-than on packed integer quadwords.
|
|
|
Compare Packed Signed Integers for Greater Than (word).
|
|
|
Packed Compare Implicit Length Strings, Return Index.
|
|
|
Packed Compare Implicit Length Strings, Return Mask.
|
|
|
Parallel deposit of bits using a mask.
|
|
|
Parallel extraction of bits using a mask.
|
|
|
Extract Byte.
|
|
|
Extract Dword.
|
|
|
Extract Qword.
|
|
|
Extract Word.
|
|
|
Packed Horizontal Add.
|
|
|
Packed Horizontal Add and Saturate.
|
|
|
Packed Horizontal Add.
|
|
|
Packed Horizontal Word Minimum.
|
|
Packed Horizontal Subtract.
|
|
|
Packed Horizontal Subtract and Saturate.
|
|
|
Packed Horizontal Subtract.
|
|
|
Insert Byte.
|
|
|
Insert a dword value from 32-bit register or memory into an XMM register.
|
|
|
Insert a qword value from 64-bit register or memory into an XMM register.
|
|
|
Insert Word.
|
|
|
Multiply and Add Packed Signed and Unsigned Bytes.
|
|
|
Multiply and Add Packed Integers.
|
|
|
Compare packed signed byte integers.
|
|
|
Compare packed signed dword integers.
|
|
|
Maximum of Packed Signed Word Integers.
|
|
|
Maximum of Packed Unsigned Byte Integers.
|
|
|
Compare packed unsigned dword integers.
|
|
|
Compare packed unsigned word integers.
|
|
|
Minimum of Packed Signed Byte Integers.
|
|
|
Compare packed signed dword integers.
|
|
|
Minimum of Packed Signed Word Integers.
|
|
|
Minimum of Packed Unsigned Byte Integers.
|
|
|
Minimum of Packed Dword Integers.
|
|
|
Compare packed unsigned word integers.
|
|
|
Move Byte Mask.
|
|
|
Packed Move with Sign Extend.
|
|
|
Packed Move with Sign Extend.
|
|
|
Packed Move with Sign Extend.
|
|
|
Packed Move with Sign Extend.
|
|
|
Packed Move with Sign Extend.
|
|
|
Packed Move with Sign Extend.
|
|
|
Packed Move with Zero Extend.
|
|
|
Packed Move with Zero Extend.
|
|
|
Packed Move with Zero Extend.
|
|
|
Packed Move with Zero Extend.
|
|
|
Packed Move with Zero Extend.
|
|
|
Packed Move with Zero Extend.
|
|
|
Multiply Packed Doubleword Integers.
|
|
|
Packed Multiply High with Round and Scale.
|
|
|
Multiply Packed Unsigned Integers and Store High Result.
|
|
|
Multiply Packed Signed Integers and Store High Result.
|
|
|
Multiply Packed Integers and Store Low Result.
|
|
|
Multiply Packed Signed Integers and Store Low Result.
|
|
|
Multiply Packed Unsigned Doubleword Integers.
|
|
|
Pop a Value from the Stack.
|
|
|
Pop All General-Purpose Registers (word).
|
|
|
Pop All General-Purpose Registers (doubleword).
|
|
|
Return the Count of Number of Bits Set to 1.
|
|
|
Pop Stack into EFLAGS Register (lower 16bits EFLAGS).
|
|
|
Pop Stack into EFLAGS Register (EFLAGS).
|
|
|
Pop Stack into EFLAGS Register (RFLAGS).
|
|
|
Bitwise Logical OR.
|
|
|
Prefetch Data Into Caches (using NTA hint).
|
|
Prefetch Data Into Caches (using T0 hint).
|
|
Prefetch Data Into Caches (using T1 hint).
|
|
Prefetch Data Into Caches (using T2 hint).
|
|
Prefetch Data into Caches in Anticipation of a Write.
|
|
|
Prefetch Vector Data Into Caches with Intent to Write and T1 Hint.
|
|
Compute Sum of Absolute Differences.
|
|
|
Packed Shuffle Bytes.
|
|
|
Shuffle Packed Doublewords.
|
|
|
Shuffle Packed High Words.
|
|
|
Shuffle Packed Low Words.
|
|
|
Shuffle Packed Words.
|
|
|
Packed Sign Byte.
|
|
|
Packed Sign Doubleword.
|
|
|
Packed Sign Word.
|
|
|
Shift Packed Data Left Logical (doubleword).
|
|
|
Shift Double Quadword Left Logical.
|
|
|
Shift Packed Data Left Logical (quadword).
|
|
|
Shift Packed Data Left Logical (word).
|
|
|
Shift Packed Data Right Arithmetic (doubleword).
|
|
|
Shift Packed Data Right Arithmetic (word).
|
|
|
Shift Packed Data Right Logical (doubleword).
|
|
|
Shift Double Quadword Right Logical.
|
|
|
Shift Packed Data Right Logical (quadword).
|
|
|
Shift Packed Data Right Logical (word).
|
|
|
Subtract Packed Integers (byte).
|
|
|
Subtract Packed Integers (doubleword).
|
|
|
Subtract Packed Integers (quadword).
|
|
|
Subtract Packed Signed Integers with Signed Saturation (byte).
|
|
|
Subtract Packed Signed Integers with Signed Saturation (word).
|
|
|
Subtract Packed Unsigned Integers with Unsigned Saturation (byte).
|
|
|
Subtract Packed Unsigned Integers with Unsigned Saturation (word).
|
|
|
Subtract Packed Integers (word).
|
|
|
Logical Compare.
|
|
|
Unpack High Data.
|
|
|
Unpack High Data.
|
|
|
Unpack High Data.
|
|
Unpack High Data.
|
|
|
Unpack Low Data.
|
|
|
Unpack Low Data.
|
|
|
Unpack Low Data.
|
|
Unpack Low Data.
|
|
|
Push Word, Doubleword or Quadword Onto the Stack.
|
|
|
Push All General-Purpose Registers (word).
|
|
|
Push All General-Purpose Registers (doubleword).
|
|
|
Push EFLAGS Register onto the Stack (16bits of EFLAGS).
|
|
|
Push EFLAGS Register onto the Stack (EFLAGS).
|
|
|
Push EFLAGS Register onto the Stack (RFLAGS).
|
|
|
Logical Exclusive OR.
|
|
|
Rotate x bits (CF, r/m(x)) left once.
|
|
|
Compute reciprocals of packed single-precision floating-point values.
|
|
|
Compute reciprocal of scalar single-precision floating-point values.
|
|
|
Rotate x bits (CF, r/m(x)) right once.
|
|
|
Read FS Segment Base.
|
|
|
Read GS Segment Base.
|
|
|
Read from Model Specific Register.
|
|
|
Read Protection Key Rights for User Pages.
|
|
|
Read Performance-Monitoring Counters.
|
|
|
Read Random Number.
|
|
|
Read Random SEED.
|
|
|
Read shadow stack point (SSP).
|
|
|
Read shadow stack point (SSP).
|
|
|
Read Time-Stamp Counter.
|
|
|
Read Time-Stamp Counter and Processor ID.
|
|
|
Repeat while ECX not zero.
|
|
|
Repeat while equal/Repeat while zero.
|
|
|
Repeat while not equal/Repeat while not zero.
|
|
|
Repeat while not equal/Repeat while not zero.
|
|
|
Repeat while equal/Repeat while zero.
|
|
|
Far return.
|
|
|
Far return w/ immediate.
|
|
|
Near return.
|
|
|
Near return w/ immediate .
|
|
Rotate x bits r/m(x) left once.
|
|
|
Rotate x bits r/m(x) right once.
|
|
|
Rotate right without affecting arithmetic flags.
|
|
|
Round Packed Double Precision Floating-Point Values.
|
|
|
Round Packed Single Precision Floating-Point Values.
|
|
|
Round Scalar Double Precision Floating-Point Values.
|
|
|
Round Scalar Single Precision Floating-Point Values.
|
|
|
Resume from System Management Mode.
|
|
|
Compute reciprocals of square roots of packed single-precision FP values.
|
|
|
Compute reciprocal of square root of scalar single-precision FP values.
|
|
|
Restore a shadow stack pointer (SSP).
|
|
|
Store AH into Flags.
|
|
|
Shift.
|
|
|
Shift arithmetic right.
|
|
|
Save previous shadow stack pointer (SSP).
|
|
Integer Subtraction with Borrow.
|
|
|
Scan String (byte).
|
|
|
Scan String (doubleword).
|
|
|
Scan String (quadword).
|
|
|
Scan String (word).
|
|
|
Set byte if above (CF = 0 and ZF = 0).
|
|
|
Set byte if below (CF = 1).
|
|
|
Set byte if below or equal (CF = 1 or ZF = 1).
|
|
|
Set byte if greater (ZF = 0 and SF = OF).
|
|
|
Set byte if less (SF <> OF).
|
|
|
Set byte if less or equal (ZF = 1 or SF <> OF).
|
|
|
Set byte if not below (CF = 0).
|
|
|
Set byte if not less (SF = OF).
|
|
|
Set byte if not overflow (OF = 0).
|
|
|
Set byte if not parity (PF = 0).
|
|
|
Set byte if not sign (SF = 0).
|
|
|
Set byte if not zero (ZF = 0).
|
|
|
Set byte if overflow (OF = 1).
|
|
|
Set byte if parity (PF = 1).
|
|
|
Set byte if sign (SF = 1).
|
|
|
Set busy bit in a supervisor shadow stack token.
|
|
|
Set byte if sign (ZF = 1).
|
|
|
Store Fence.
|
|
|
Store Global Descriptor Table Register.
|
|
|
Perform an Intermediate Calculation for the Next Four SHA1 Message Dwords.
|
|
|
Perform a Final Calculation for the Next Four SHA1 Message Dwords.
|
|
|
Calculate SHA1 state E after four rounds.
|
|
|
Perform four rounds of SHA1 operations.
|
|
|
Perform an intermediate calculation for the next 4 SHA256 message dwords.
|
|
Perform the final calculation for the next four SHA256 message dwords.
|
|
Perform two rounds of SHA256 operations.
|
|
Shift.
|
|
|
Double Precision Shift Left.
|
|
|
Shift logic left.
|
|
|
Shift.
|
|
|
Double Precision Shift Right.
|
|
|
Shift logic right.
|
|
|
Shuffle Packed Double-Precision Floating-Point Values.
|
|
|
Shuffle Packed Single-Precision Floating-Point Values.
|
|
|
Store Interrupt Descriptor Table Register.
|
|
|
Store Local Descriptor Table Register.
|
|
|
Store Machine Status Word.
|
|
|
Compute packed square roots of packed double-precision FP values.
|
|
|
Compute square roots of packed single-precision floating-point values.
|
|
|
Compute scalar square root of scalar double-precision FP values.
|
|
|
Compute square root of scalar single-precision floating-point values.
|
|
|
Set AC Flag in EFLAGS Register.
|
|
|
Set Carry Flag.
|
|
|
Set Direction Flag.
|
|
|
Set Interrupt Flag.
|
|
|
Store MXCSR Register State.
|
|
|
Store String (store AL).
|
|
|
Store String (store EAX).
|
|
|
Store String (store RAX).
|
|
|
Store String (store AX).
|
|
|
Store Task Register.
|
|
|
Subtract.
|
|
|
Subtract Packed Double-Precision Floating-Point Values.
|
|
|
Subtract Packed Single-Precision Floating-Point Values.
|
|
|
Subtract Scalar Double-Precision Floating-Point Values.
|
|
|
Subtract Scalar Single-Precision Floating-Point Values.
|
|
|
Swap GS Base Register.
|
|
|
Fast System Call.
|
|
|
Fast System Call.
|
|
|
Fast Return from Fast System Call.
|
|
|
Return From Fast System Call.
|
|
|
Logical Compare.
|
|
|
Count the Number of Trailing Zero Bits.
|
|
|
Unordered Compare Scalar Double-Precision FP Values and Set EFLAGS.
|
|
|
Unordered Compare Scalar Single-Precision FPValues and Set EFLAGS.
|
|
|
Undefined instruction.
|
|
|
Undefined Instruction (Raise invalid opcode exception).
|
|
|
Unpack and Interleave High Packed Double-Precision Floating-Point Values.
|
|
|
Unpack and Interleave High Packed Single-Precision Floating-Point Values.
|
|
|
Unpack and Interleave Low Packed Double-Precision Floating-Point Values.
|
|
|
Unpack and Interleave Low Packed Single-Precision Floating-Point Values.
|
|
|
Add Packed Double-Precision Floating-Point Values.
|
|
|
Add Packed Double-Precision Floating-Point Values.
|
|
|
Add Scalar Double-Precision Floating-Point Values.
|
|
|
Add Scalar Single-Precision Floating-Point Values.
|
|
|
Perform dword alignment of two concatenated source vectors.
|
|
|
Perform qword alignment of two concatenated source vectors.
|
|
|
Bitwise Logical AND of Packed Double-Precision Floating-Point Values.
|
|
|
Bitwise Logical AND of Packed Single-Precision Floating-Point Values.
|
|
|
Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values.
|
|
|
Bitwise Logical AND NOT of Packed Single-Precision Floating-Point Values.
|
|
|
Replace the VBLENDVPD instructions (using opmask as select control).
|
|
|
Replace the VBLENDVPS instructions (using opmask as select control).
|
|
|
Variable Blend Packed Double-Precision Floats.
|
|
|
Broadcast 128 bits of int data in mem to low and high 128-bits in ymm1.
|
|
Broadcast low double-precision floating-point element.
|
|
Broadcast Floating-Point Data.
|
|
Compare Packed Double-Precision Floating-Point Values.
|
|
|
Compare Packed Single-Precision Floating-Point Values.
|
|
|
Compare Scalar Double-Precision Floating-Point Values.
|
|
|
Scalar Single-Precision Floating-Point Values.
|
|
|
Compare Scalar Ordered Double-Precision FP Values and Set EFLAGS.
|
|
|
Compare Scalar Ordered Single-Precision FP Values and Set EFLAGS.
|
|
|
Compress packed DP elements of a vector.
|
|
Compress packed SP elements of a vector.
|
|
Convert two packed signed doubleword integers.
|
|
|
Convert Packed Dword Integers to Packed Single-Precision FP Values.
|
|
|
Convert two packed double-precision floating-point values.
|
|
|
Convert Packed Double-Precision FP Values to Packed Quadword Integers.
|
|
|
Convert Packed DP FP Values to Packed Unsigned DWord Integers.
|
|
Convert Packed DP FP Values to Packed Unsigned QWord Integers.
|
|
Convert 16-bit FP values to Single-Precision FP values.
|
|
|
Convert Packed Single-Precision FP Values to Packed Dbl-Precision FP Values.
|
|
|
Convert Single-Precision FP value to 16-bit FP value.
|
|
|
Convert Packed SP FP Values to Packed Signed QWord Int Values.
|
|
|
Convert Packed SP FP Values to Packed Unsigned DWord Int Values.
|
|
Convert Packed SP FP Values to Packed Unsigned QWord Int Values.
|
|
Convert Packed Quadword Integers to Packed Double-Precision FP Values.
|
|
|
Convert Packed Quadword Integers to Packed Single-Precision FP Values.
|
|
|
Convert Scalar Double-Precision FP Value to Integer.
|
|
|
Convert Scalar Double-Precision FP Val to Scalar Single-Precision FP Val.
|
|
|
Convert Scalar Double-Precision FP Value to Unsigned Doubleword Integer.
|
|
Convert Dword Integer to Scalar Double-Precision FP Value.
|
|
|
Convert Dword Integer to Scalar Single-Precision FP Value.
|
|
|
Convert Scalar Single-Precision FP Val to Scalar Double-Precision FP Val.
|
|
|
Convert Scalar Single-Precision FP Value to Dword Integer.
|
|
|
Convert Scalar Single-Precision FP Value to Unsigned Doubleword Integer.
|
|
Convert with Trunc Packed Double-Precision FP Val to Packed Dword Integers.
|
|
Convert with Truncation Packed DP FP Values to Packed QWord Integers.
|
|
Convert with Truncation Packed DP FP Values to Packed Unsigned DWord Int.
|
|
Convert with Truncation Packed DP FP Values to Packed Unsigned QWord Int.
|
|
Convert with Truncation Packed SP FP Values to Packed Signed QWord Int.
|
|
Convert with Truncation Packed SP FP Values to Packed Unsigned DWord Int.
|
|
Convert with Truncation Packed SP FP Values to Packed Unsigned QWord Int.
|
|
Convert with Truncation Scalar Double-Precision FP Value to Signed.
|
|
Convert with Truncation Scalar DP FP Value to Unsigned Integer.
|
|
Convert with Truncation Scalar Single-Precision FP Value to Dword Integer.
|
|
Convert with Truncation Scalar Single-Precision FP Value to Unsigned Int.
|
|
Convert Packed Unsigned DWord Integers to Packed DP FP Values.
|
|
Convert Packed Unsigned DWord Integers to Packed SP FP Values.
|
|
Convert Packed Unsigned QWord Integers to Packed DP FP Values.
|
|
Convert Packed Unsigned QWord Integers to Packed SP FP Values.
|
|
Convert an unsigned integer to the low DP FP elem and merge to a vector.
|
|
Convert an unsigned integer to the low SP FP elem and merge to a vector.
|
|
Double Block Packed Sum-Absolute-Differences (SAD) on Unsigned Bytes.
|
|
|
Divide Packed Double-Precision Floating-Point Values.
|
|
|
Divide Packed Single-Precision Floating-Point Values.
|
|
|
Divide Scalar Double-Precision Floating-Point Values.
|
|
|
Divide Scalar Single-Precision Floating-Point Values.
|
|
|
Verify a Segment for Reading.
|
|
|
Verify a Segment for Writing.
|
|
|
Compute approximate base-2 exponential of packed DP FP elems of a vector.
|
|
|
Compute approximate base-2 exponential of packed SP FP elems of a vector.
|
|
|
Compute approximate base-2 exponential of the low DP FP elem of a vector.
|
|
|
Compute approximate base-2 exponential of the low SP FP elem of a vector.
|
|
|
Load Sparse Packed Double-Precision FP Values from Dense Memory.
|
|
|
Load Sparse Packed Single-Precision FP Values from Dense Memory.
|
|
|
Extract Packed Floating-Point Values.
|
|
Extract a vector from a full-length vector with 32-bit granular update.
|
|
Extract a vector from a full-length vector with 32-bit granular update.
|
|
Extract a vector from a full-length vector with 64-bit granular update.
|
|
Extract a vector from a full-length vector with 64-bit granular update.
|
|
Extract a vector from a full-length vector with 32-bit granular update.
|
|
Extract a vector from a full-length vector with 32-bit granular update.
|
|
Extract a vector from a full-length vector with 64-bit granular update.
|
|
Extract a vector from a full-length vector with 64-bit granular update.
|
|
Fix Up Special Packed Float64 Values.
|
|
Fix Up Special Packed Float32 Values.
|
|
Fix Up Special Scalar Float64 Value.
|
|
Fix Up Special Scalar Float32 Value.
|
|
Fused Multiply-Add of Packed Double-Precision Floating-Point Values.
|
|
Fused Multiply-Add of Scalar Double-Precision Floating-Point Values.
|
|
Fused Multiply-Add of Scalar Single-Precision Floating-Point Values.
|
|
Fused Multiply-Add of Packed Double-Precision Floating-Point Values.
|
|
Fused Multiply-Add of Packed Single-Precision Floating-Point Values.
|
|
Fused Multiply-Add of Scalar Double-Precision Floating-Point Values.
|
|
Fused Multiply-Add of Scalar Single-Precision Floating-Point Values.
|
|
Fused Multiply-Add of Packed Double-Precision Floating-Point Value.
|
|
Fused Multiply-Add of Scalar Double-Precision Floating-Point Values.
|
|
Fused Multiply-Add of Scalar Single-Precision Floating-Point Values.
|
|
Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values.
|
|
Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values.
|
|
Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values.
|
|
Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values.
|
|
Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values.
|
|
Fused Negative Multiply-Add of Packed Double-Precision FP Values.
|
|
Fused Negative Multiply-Add of Scalar Double-Precision FP Values.
|
|
Fused Negative Multiply-Add of Packed Double-Precision FP Values.
|
|
Fused Negative Multiply-Add of Scalar Double-Precision FP Values.
|
|
Fused Negative Multiply-Add of Packed Double-Precision FP Values.
|
|
Fused Negative Multiply-Add of Scalar Double-Precision FP Values.
|
|
Tests Types Of a Packed Float64 Values.
|
|
Tests Types Of a Packed Float32 Values.
|
|
Tests Types Of a Scalar Float64 Values.
|
|
Tests Types Of a Scalar Float32 Values.
|
|
Gather Packed SP FP values Using Signed Dword/Qword Indices.
|
|
Gather Packed DP FP Values Using Signed Dword/Qword Indices.
|
|
Convert Exponents of Packed DP FP Values to DP FP Values.
|
|
|
Convert Exponents of Packed SP FP Values to SP FP Values.
|
|
|
Convert Exponents of Scalar DP FP Values to DP FP Value.
|
|
|
Convert Exponents of Scalar SP FP Values to SP FP Value.
|
|
|
Extract Float64 Vector of Normalized Mantissas from Float64 Vector.
|
|
Extract Float32 Vector of Normalized Mantissas from Float32 Vector.
|
|
Extract Float64 of Normalized Mantissas from Float64 Scalar.
|
|
Extract Float32 Vector of Normalized Mantissa from Float32 Vector.
|
|
Insert Packed Floating-Point Values.
|
|
Insert Packed Floating-Point Values.
|
|
Insert Packed Floating-Point Values.
|
|
Insert Packed Floating-Point Values.
|
|
Insert Packed Integer Values.
|
|
Insert 256 bits of packed doubleword integer values.
|
|
Insert Packed Floating-Point Values.
|
|
Insert 256 bits of packed quadword integer values.
|
|
Load Unaligned Integer 128 Bits.
|
|
|
Return Maximum Packed Double-Precision Floating-Point Values.
|
|
|
Maximum of Packed Single-Precision Floating-Point Values.
|
|
|
Return Maximum Scalar Double-Precision Floating-Point Value.
|
|
|
Return Maximum Scalar Single-Precision Floating-Point Value.
|
|
|
Call to VM Monitor.
|
|
|
Clear Virtual-Machine Control Structure.
|
|
|
Invoke VM function.
|
|
|
Return Minimum Packed Double-Precision Floating-Point Values.
|
|
|
Return Minimum Packed Single-Precision Floating-Point Values.
|
|
|
Return Minimum Scalar Double-Precision Floating-Point Value.
|
|
|
Return Minimum Scalar Single-Precision Floating-Point Value.
|
|
|
Launch Virtual Machine.
|
|
|
Move Aligned Packed Double-Precision Floating-Point Values.
|
|
|
Move Aligned Packed Single-Precision Floating-Point Values.
|
|
|
Move Doubleword.
|
|
|
Move One Double-FP and Duplicate.
|
|
|
Move Aligned Double Quadword.
|
|
|
Move Aligned Double Quadword.
|
|
|
Move Aligned Double Quadword.
|
|
|
Move Unaligned Double Quadword.
|
|
|
VMOVDQU with 16-bit granular conditional update.
|
|
|
Move Unaligned Double Quadword.
|
|
|
Move Unaligned Double Quadword.
|
|
|
VMOVDQU with 8-bit granular conditional update.
|
|
|
Move Packed Single-Precision Floating-Point Values High to Low.
|
|
|
Move High Packed Double-Precision Floating-Point Value.
|
|
|
Move High Packed Single-Precision Floating-Point Values.
|
|
|
Move Packed Single-Precision Floating-Point Values Low to High.
|
|
|
Move Low Packed Double-Precision Floating-Point Value.
|
|
|
Move Low Packed Single-Precision Floating-Point Values.
|
|
|
Extract Packed Double-Precision Floating-Point Sign Mask.
|
|
|
Extract Packed Single-Precision Floating-Point Sign Mask.
|
|
|
Load Double Quadword Non-Temporal Aligned Hint.
|
|
|
Store Packed Double-Precision FP Values Using Non-Temporal Hint.
|
|
|
Store Packed Single-Precision FP Values Using Non-Temporal Hint.
|
|
|
Move Quadword.
|
|
|
Move Data from String to String (doubleword).
|
|
|
Move Packed Single-FP High and Duplicate.
|
|
|
Move Packed Single-FP Low and Duplicate.
|
|
|
Move Scalar Single-Precision Floating-Point Values.
|
|
|
Move Unaligned Packed Double-Precision Floating-Point Values.
|
|
|
Move Unaligned Packed Single-Precision Floating-Point Values.
|
|
|
Load Pointer to Virtual-Machine Control Structure.
|
|
|
Store Pointer to Virtual-Machine Control Structure.
|
|
|
Reads a component from the VMCS and stores it into a destination operand.
|
|
|
Resume Virtual Machine.
|
|
|
Multiply Packed Double-Precision Floating-Point Values.
|
|
|
Multiply Packed Single-Precision Floating-Point Values.
|
|
|
Multiply Scalar Double-Precision Floating-Point Values.
|
|
|
Multiply Scalar Single-Precision Floating-Point Values.
|
|
|
Writes a component to the VMCS from a source operand.
|
|
|
Leave VMX Operation.
|
|
|
Enter VMX Operation.
|
|
|
Bitwise Logical OR of Double-Precision Floating-Point Values.
|
|
|
Bitwise Logical OR of Single-Precision Floating-Point Values.
|
|
|
Packed Absolute Value (byte).
|
|
|
Packed Absolute Value (dword).
|
|
|
Packed Absolute Value (word).
|
|
|
Pack with Signed Saturation.
|
|
|
Pack with Signed Saturation.
|
|
|
Pack with Unsigned Saturation.
|
|
|
Pack with Unsigned Saturation.
|
|
|
Add Packed byte Integers.
|
|
|
Add Packed Doubleword Integers.
|
|
|
Add Packed Quadword Integers.
|
|
|
Add Packed Signed Integers with Signed Saturation (byte).
|
|
|
Add Packed Signed Integers with Signed Saturation (word).
|
|
|
Add Packed Unsigned Integers with Unsigned Saturation (byte).
|
|
|
Add Packed Unsigned Integers with Unsigned Saturation (word).
|
|
|
Add Packed word Integers.
|
|
|
Packed Align Right.
|
|
|
Logical AND.
|
|
|
Logical AND NOT.
|
|
|
Average Packed Integers (byte).
|
|
|
Average Packed Integers (word).
|
|
|
Blend Byte/Word Vectors Using an Opmask Control.
|
|
|
Blend Int32/Int64 Vectors Using an OpMask Control.
|
|
|
Blend qword elements using opmask as select control.
|
|
|
Blend word elements using opmask as select control.
|
|
|
Broadcast Integer Data.
|
|
Broadcast from general-purpose register to vector register.
|
|
Broadcast Mask to Vector Register.
|
|
Broadcast from general-purpose register to vector register.
|
|
Broadcast from general-purpose register to vector register.
|
|
Compare packed signed bytes using specified primitive.
|
|
|
Compare packed signed dwords using specified primitive.
|
|
|
Compare Packed Data for Equal (byte).
|
|
|
Compare Packed Data for Equal (doubleword).
|
|
|
Compare Packed Data for Equal (quadword).
|
|
|
Compare Packed Data for Equal (word).
|
|
|
Packed Compare Explicit Length Strings, Return Index.
|
|
Packed Compare Explicit Length Strings, Return Mask.
|
|
Compare Packed Signed Integers for Greater Than (byte).
|
|
|
Compare Packed Signed Integers for Greater Than (doubleword).
|
|
|
Compare Packed Data for Greater Than (qword).
|
|
|
Compare Packed Signed Integers for Greater Than (word).
|
|
|
Packed Compare Implicit Length Strings, Return Index.
|
|
Packed Compare Implicit Length Strings, Return Mask.
|
|
Compare packed signed quadwords using specified primitive.
|
|
|
Compare packed signed words using specified primitive.
|
|
|
Compare packed unsigned bytes using specified primitive.
|
|
|
Compare packed unsigned dwords using specified primitive.
|
|
|
Compare packed unsigned quadwords using specified primitive.
|
|
|
Compare packed unsigned words using specified primitive.
|
|
|
Store Sparse Packed Doubleword Integer Values into Dense Memory/Register.
|
|
Store Sparse Packed Quadword Integer Values into Dense Memory/Register.
|
|
Detect conflicts within a vector of packed 32/64-bit integers.
|
|
Detect conflicts within a vector of packed 64-bit integers.
|
|
Full Permute of Bytes from Two Tables Overwriting the Index.
|
|
|
Full permute of two tables of dword elements overwriting the index vector.
|
|
|
Full permute of two tables of DP elements overwriting the index vector.
|
|
|
Full permute of two tables of SP elements overwriting the index vector.
|
|
|
Full permute of two tables of qword elements overwriting the index vector.
|
|
|
Full Permute From Two Tables Overwriting the Index.
|
|
|
Full permute of two tables of dword elements overwriting one source table.
|
|
|
Full permute of two tables of DP elements overwriting one source table.
|
|
|
Full permute of two tables of SP elements overwriting one source table.
|
|
|
Full permute of two tables of qword elements overwriting one source table.
|
|
|
Permute packed word elements.
|
|
|
Load Sparse Packed Doubleword Integer Values from Dense Memory / Register.
|
|
|
Load Sparse Packed Quadword Integer Values from Dense Memory / Register.
|
|
|
Extract DWord.
|
|
|
Extract Word.
|
|
|
Gather packed dword values using signed Dword/Qword indices.
|
|
Packed Horizontal Add (32-bit).
|
|
|
Packed Horizontal Add and Saturate (16-bit).
|
|
|
Packed Horizontal Add (16-bit).
|
|
|
Packed Horizontal Word Minimum.
|
|
Packed Horizontal Subtract (32-bit).
|
|
|
Packed Horizontal Subtract and Saturate (16-bit).
|
|
|
Packed Horizontal Subtract (16-bit).
|
|
|
Insert Byte.
|
|
|
Insert Dword.
|
|
|
Insert Qword.
|
|
|
Insert Word.
|
|
|
Count the number of leading zero bits of packed dword elements.
|
|
|
Count the number of leading zero bits of packed qword elements.
|
|
|
Multiply and Add Packed Integers.
|
|
|
Maximum of Packed Signed Integers (byte).
|
|
|
Maximum of Packed Signed Integers (dword).
|
|
|
Compute maximum of packed signed 64-bit integer elements.
|
|
|
Maximum of Packed Signed Word Integers.
|
|
|
Maximum of Packed Unsigned Byte Integers.
|
|
|
Maximum of Packed Unsigned Integers (dword).
|
|
|
Compute maximum of packed unsigned 64-bit integer elements.
|
|
|
Maximum of Packed Unsigned Integers (word).
|
|
|
Minimum of Packed Signed Integers (byte).
|
|
|
Minimum of Packed Signed Integers (dword).
|
|
|
Compute minimum of packed signed 64-bit integer elements.
|
|
|
Minimum of Packed Signed Word Integers.
|
|
|
Minimum of Packed Unsigned Byte Integers.
|
|
|
Minimum of Packed Dword Integers.
|
|
|
Compute minimum of packed unsigned 64-bit integer elements.
|
|
|
Minimum of Packed Unsigned Integers (word).
|
|
|
Convert a vector register in 32/64-bit granularity to an opmask register.
|
|
|
Convert a Vector Register to a Mask.
|
|
|
Down Convert DWord to Byte.
|
|
|
Down Convert DWord to Word.
|
|
|
Convert opmask register to vector register in 8-bit granularity.
|
|
|
Convert opmask register to vector register in 32-bit granularity.
|
|
|
Convert opmask register to vector register in 64-bit granularity.
|
|
|
Convert opmask register to vector register in 16-bit granularity.
|
|
|
Move Byte Mask.
|
|
|
Convert a Vector Register to a Mask.
|
|
|
Down Convert QWord to Byte.
|
|
|
Down Convert QWord to DWord.
|
|
|
Down Convert QWord to Word.
|
|
|
Down Convert DWord to Byte.
|
|
|
Down Convert DWord to Word.
|
|
|
Down Convert QWord to Byte.
|
|
|
Down Convert QWord to Dword.
|
|
|
Down Convert QWord to Word.
|
|
|
Down Convert Word to Byte.
|
|
|
Packed Move with Sign Extend (8-bit to 32-bit).
|
|
|
Packed Move with Sign Extend (8-bit to 64-bit).
|
|
|
Packed Move with Sign Extend (8-bit to 16-bit).
|
|
|
Packed Move with Sign Extend (32-bit to 64-bit).
|
|
|
Packed Move with Sign Extend (16-bit to 32-bit).
|
|
|
Packed Move with Sign Extend (16-bit to 64-bit).
|
|
|
Down Convert DWord to Byte.
|
|
|
Down Convert DWord to Word.
|
|
|
Down Convert QWord to Byte.
|
|
|
Down Convert QWord to DWord.
|
|
|
Down Convert QWord to Word.
|
|
|
Down Convert Word to Byte.
|
|
|
Convert a vector register in 16-bit granularity to an opmask register.
|
|
|
Down convert word elements in a vector to byte elements using truncation.
|
|
|
Packed Move with Zero Extend (8-bit to 32-bit).
|
|
|
Packed Move with Zero Extend (8-bit to 64-bit).
|
|
|
Packed Move with Zero Extend (8-bit to 16-bit).
|
|
|
Packed Move with Zero Extend (32-bit to 64-bit).
|
|
|
Packed Move with Zero Extend (16-bit to 32-bit).
|
|
|
Packed Move with Zero Extend (16-bit to 64-bit).
|
|
|
Multiply Packed Doubleword Integers.
|
|
|
Packed Multiply High with Round and Scale.
|
|
|
Multiply Packed Unsigned Integers and Store High Result.
|
|
|
Multiply Packed Signed Integers and Store High Result.
|
|
|
Multiply Packed Integers and Store Low Result.
|
|
|
Multiply Packed Integers and Store Low Result.
|
|
|
Multiply Packed Signed Integers and Store Low Result.
|
|
|
Multiply Packed Unsigned Doubleword Integers.
|
|
|
Bitwise Logical OR.
|
|
|
Rotate dword elem left by a constant shift count with conditional update.
|
|
|
Rotate qword elem left by a constant shift count with conditional update.
|
|
|
Rotate dword element left by shift counts specified.
|
|
|
Rotate qword element left by shift counts specified.
|
|
|
Rotate dword element right by a constant shift count.
|
|
|
Rotate qword element right by a constant shift count.
|
|
|
Rotate dword element right by shift counts specified.
|
|
|
Rotate qword element right by shift counts specified.
|
|
|
Compute Sum of Absolute Differences.
|
|
|
Scatter dword elements in a vector to memory using dword indices.
|
|
Scatter qword elements in a vector to memory using dword indices.
|
|
Scatter dword elements in a vector to memory using qword indices.
|
|
Scatter qword elements in a vector to memory using qword indices.
|
|
Packed Shuffle Bytes.
|
|
|
Shuffle Packed Doublewords.
|
|
|
Shuffle Packed High Words.
|
|
|
Shuffle Packed Low Words.
|
|
|
Packed SIGN (byte).
|
|
|
Packed SIGN (doubleword).
|
|
|
Packed SIGN (word).
|
|
|
Shift Packed Data Left Logical (doubleword).
|
|
|
Shift Double Quadword Left Logical.
|
|
|
Shift Packed Data Left Logical (quadword).
|
|
|
Variable Bit Shift Left Logical.
|
|
|
Shift Packed Data Left Logical (word).
|
|
|
Shift Packed Data Right Arithmetic (doubleword).
|
|
|
Shift qwords right by a constant shift count and shifting in sign bits.
|
|
|
Shift qwords right by shift counts in a vector and shifting in sign bits.
|
|
|
Variable Bit Shift Right Arithmetic.
|
|
|
Shift Packed Data Right Arithmetic (word).
|
|
|
Shift Packed Data Right Logical (doubleword).
|
|
|
Shift Double Quadword Right Logical.
|
|
|
Shift Packed Data Right Logical (quadword).
|
|
|
Variable Bit Shift Right Logical.
|
|
|
Shift Packed Data Right Logical (word).
|
|
|
Subtract Packed Integers (byte).
|
|
|
Subtract Packed Integers (doubleword).
|
|
|
Subtract Packed Integers (quadword).
|
|
|
Subtract Packed Signed Integers with Signed Saturation (byte).
|
|
|
Subtract Packed Signed Integers with Signed Saturation (word).
|
|
|
Subtract Packed Unsigned Integers with Unsigned Saturation (byte).
|
|
|
Subtract Packed Unsigned Integers with Unsigned Saturation (word).
|
|
|
Subtract Packed Integers (word).
|
|
|
Perform bitwise ternary logic operation of three vectors.
|
|
|
Perform bitwise ternary logic operation of three vectors.
|
|
|
Bitwise Ternary Logic.
|
|
Logical Compare.
|
|
|
Perform bitwise AND of byte elems of two vecs and write results to opmask.
|
|
|
Perform bitwise AND of dword elems of 2-vecs and write results to opmask.
|
|
|
Perform bitwise AND of qword elems of 2-vecs and write results to opmask.
|
|
|
Perform bitwise AND of word elems of two vecs and write results to opmask.
|
|
|
Perform bitwise NAND of byte elems of 2-vecs and write results to opmask.
|
|
|
Perform bitwise NAND of dword elems of 2-vecs and write results to opmask.
|
|
|
Perform bitwise NAND of qword elems of 2-vecs and write results to opmask.
|
|
|
Perform bitwise NAND of word elems of 2-vecs and write results to opmask.
|
|
|
Unpack High Data.
|
|
Unpack High Data.
|
|
Unpack High Data.
|
|
Unpack High Data.
|
|
Unpack Low Data.
|
|
Unpack Low Data.
|
|
Unpack Low Data.
|
|
Unpack Low Data.
|
|
Logical Exclusive OR.
|
|
|
Bitwise XOR of packed doubleword integers.
|
|
|
Bitwise XOR of packed quadword integers.
|
|
|
Range Restriction Calculation For Packed Pairs of Float64 Values.
|
|
|
Range Restriction Calculation For Packed Pairs of Float32 Values.
|
|
|
Range Restriction Calculation From a pair of Scalar Float64 Values.
|
|
|
Range Restriction Calculation From a Pair of Scalar Float32 Values.
|
|
|
Compute Approximate Reciprocals of Packed Float64 Values.
|
|
|
Compute Approximate Reciprocals of Packed Float32 Values.
|
|
|
Compute Approximate Reciprocal of Scalar Float64 Value.
|
|
|
Compute Approximate Reciprocal of Scalar Float32 Value.
|
|
|
Computes the reciprocal approximation of the float64 values.
|
|
|
Computes the reciprocal approximation of the float32 values.
|
|
|
Computes the reciprocal approximation of the low float64 value.
|
|
|
Computes the reciprocal approximation of the low float32 value.
|
|
|
Compute reciprocals of packed single-precision floating-point values.
|
|
|
Compute Reciprocal of Scalar Single-Precision Floating-Point Values.
|
|
|
Perform Reduction Transformation on Packed Float64 Values.
|
|
|
Perform Reduction Transformation on Packed Float32 Values.
|
|
|
Perform a Reduction Transformation on a Scalar Float64 Value.
|
|
|
Perform a Reduction Transformation on a Scalar Float32 Value.
|
|
|
Round Packed Float64 Values To Include A Given Number Of Fraction Bits.
|
|
Round Packed Float32 Values To Include A Given Number Of Fraction Bits.
|
|
Round Scalar Float64 Value To Include A Given Number Of Fraction Bits.
|
|
Round Scalar Float32 Value To Include A Given Number Of Fraction Bits.
|
|
Round Packed Double-Precision Values.
|
|
|
Round Packed Single-Precision Values.
|
|
|
Round Scalar Double-Precision Value.
|
|
|
Compute Approximate Reciprocals of Square Roots of Packed Float64 Values.
|
|
Compute Approximate Reciprocals of Square Roots of Packed Float32 Values.
|
|
Compute Approximate Reciprocal of Square Root of Scalar Float64 Value.
|
|
Compute Approximate Reciprocal of Square Root of Scalar Float32 Value.
|
|
Computes the reciprocal square root of the float64 values.
|
|
Computes the reciprocal square root of the float32 values.
|
|
Computes the reciprocal square root of the low float64 value.
|
|
Computes the reciprocal square root of the low float32 value.
|
|
Compute Reciprocals of Square Roots of Packed Single-Precision FP Values.
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Compute Reciprocal of Square Root of Scalar Single-Precision FP Value.
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Multiply packed DP FP elements of a vector by powers.
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Multiply packed SP FP elements of a vector by powers.
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Multiply the low DP FP element of a vector by powers.
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Multiply the low SP FP element of a vector by powers.
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Scatter SP/DP FP elements in a vector to memory using dword indices.
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Scatter SP/DP FP elements in a vector to memory using dword indices.
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Scatter SP/DP FP elements in a vector to memory using qword indices.
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Scatter SP/DP FP elements in a vector to memory using qword indices.
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Shuffle 128-bit lanes of a vector with 32 bit granular conditional update.
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Shuffle 128-bit lanes of a vector with 64 bit granular conditional update.
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Shuffle 128-bit lanes of a vector with 32 bit granular conditional update.
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Shuffle 128-bit lanes of a vector with 64 bit granular conditional update.
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Shuffle Packed Double-Precision Floating-Point Values.
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Shuffle Packed Single-Precision Floating-Point Values.
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Compute packed square roots of packed double-precision FP values.
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Compute square roots of packed single-precision floating-point values.
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Compute scalar square root of scalar double-precision FP values.
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Compute square root of scalar single-precision floating-point values.
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Subtract Packed Double-Precision Floating-Point Values.
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Subtract Packed Single-Precision Floating-Point Values.
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Subtract Scalar Double-Precision Floating-Point Values.
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Subtract Scalar Single-Precision Floating-Point Values.
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Unordered Compare Scalar Double-Precision FP Values and Set EFLAGS.
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Unordered Compare Scalar Single-Precision FPValues and Set EFLAGS.
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Unpack and Interleave High Packed Double-Precision Floating-Point Values.
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Unpack and Interleave High Packed Single-Precision Floating-Point Values.
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Unpack and Interleave Low Packed Double-Precision Floating-Point Values.
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Unpack and Interleave Low Packed Single-Precision Floating-Point Values.
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Bitwise Logical XOR for Double-Precision Floating-Point Values.
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Bitwise Logical XOR for Single-Precision Floating-Point Values.
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Zero Upper Bits of YMM Registers.
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Wait.
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Write Back and Invalidate Cache.
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Write FS Segment Base.
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Write GS Segment Base.
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Write to Model Specific Register.
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Write Data to User Page Key Register.
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Write to a shadow stack.
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Write to a shadow stack.
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Write to a user mode shadow stack.
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Write to a user mode shadow stack.
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Transactional Abort.
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Prefix hint to the beginning of an HLE transaction region.
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Exchange and Add.
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Transactional Begin.
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Exchange Register/Memory with Register.
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Transactional End.
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Value of Extended Control Register.
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Table lookup translation.
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Table Look-up Translation.
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Logical Exclusive OR.
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Bitwise Logical XOR for Double-Precision Floating-Point Values.
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Bitwise Logical XOR for Single-Precision Floating-Point Values.
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Prefix hint to the end of an HLE transaction region.
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Restore Processor Extended States.
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Restore processor supervisor-mode extended states from memory.
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Restore processor supervisor-mode extended states from memory.
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Save Processor Extended States.
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Save processor extended states with compaction to memory.
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Save processor extended states with compaction to memory.
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Save Processor Extended States Optimized.
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Save processor supervisor-mode extended states to memory.
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Save processor supervisor-mode extended states to memory.
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Set Extended Control Register.
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Test If In Transactional Execution.
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