Displacement.

The internal representation for an Intel instruction used by our disassembler and lifter.

Parser for Intel (x86 or x86-64) instructions. Parser will return a platform-agnostic instruction type (Instruction).

Translation context for Intel (x86 or x86-64) instructions.

Jump target of a branch instruction.

Mandatory prefixes. The 66H, F2H, and F3H prefixes are mandatory for opcode extensions.

Intel opcodes. This type should be generated using scripts/genOpcode.fsx from the `IntelSupportedOpcodes.txt` file.

We define four different types of X86 operands: register, memory, direct address, and immediate.

A set of operands in an X86 instruction.

Opcode groups defined in manual Vol 2. Table A-6.

Operand descriptor, which describes the shape of operands in an instruction.

Instruction prefixes.

We define 8 different RegGrp types. Intel instructions use an integer value such as a REG field of a ModR/M value.

This module exposes several useful functions to handle Intel registers.

Registers for x86 (and x86-64).

Internally, a Register is represented with an integer (we use only 22 bits). The most significant 10 bits (from 12th to 21th bits) represent the size of the register. The next 4 bits (from 8th to 11th bits) represent the register kind, and the reset of 8 bits are used to represent a register ID. There are currently 13 kinds of registers including GP, FPU, MMX, etc.

 21 ... 13 12 11 10 09 08 07 06 05 04 03 02 01 00 (bit position)
 +------------+----------+----------------------+
 |  Size      | Kind     |  Register ID.        |
 +------------+----------+----------------------+

REX prefixes.

The scale of Scaled Index.

Scaled index.

Specific conditions for determining the size of operands. (See Table A-1, Appendix A.2.5 of Vol. 2D).

This exception occurs when an UnknownReg is explicitly used. This exception should not happen in general.

Information about Intel vector extension.

Types of VEX (Vector Extension).

Vector destination merging/zeroing: P[23] encodes the destination result behavior which either zeroes the masked elements or leave masked element unchanged.