Register Type
Represents registers for ARMv7, ARMv8 AArch32.
Record fields
| Record Field |
Description
|
Application Program Status Register.
|
|
C0.
|
|
C1.
|
|
C10.
|
|
C11.
|
|
C12.
|
|
C13.
|
|
C14.
|
|
C15.
|
|
C2.
|
|
C3.
|
|
C4.
|
|
C5.
|
|
C6.
|
|
C7.
|
|
C8.
|
|
C9.
|
|
Current Program Status Register.
|
|
D0.
|
|
D1.
|
|
D10.
|
|
D11.
|
|
D12.
|
|
D13.
|
|
D14.
|
|
D15.
|
|
D16.
|
|
D17.
|
|
D18.
|
|
D19.
|
|
D2.
|
|
D20.
|
|
D21.
|
|
D22.
|
|
D23.
|
|
D24.
|
|
D25.
|
|
D26.
|
|
D27.
|
|
D28.
|
|
D29.
|
|
D3.
|
|
D30.
|
|
D31.
|
|
D4.
|
|
D5.
|
|
D6.
|
|
D7.
|
|
D8.
|
|
D9.
|
|
ELRhyp.
|
|
FP.
|
|
FPINST2.
|
|
FPSCR, Floating-point Status and Control Register, VMSA.
|
|
IP.
|
|
LR, the link register.
|
|
LRabt.
|
|
LRfiq.
|
|
LRirq.
|
|
LRmon.
|
|
LRsvc.
|
|
LRund.
|
|
LRusr.
|
|
MVFR0.
|
|
MVFR1.
|
|
Non-Secure Access Control Register.
|
|
P0.
|
|
P1.
|
|
P10.
|
|
P11.
|
|
P12.
|
|
P13.
|
|
P14.
|
|
P15.
|
|
P2.
|
|
P3.
|
|
P4.
|
|
P5.
|
|
P6.
|
|
P7.
|
|
P8.
|
|
P9.
|
|
PC, the program counter.
|
|
Q0.
|
|
Q0A is the 1st 64-bit chunk of Q0A.
|
|
Q0B is the 2nd 64-bit chunk of Q0B.
|
|
Q1.
|
|
Q10.
|
|
Q10A is the 1st 64-bit chunk of Q10A.
|
|
Q10B is the 2nd 64-bit chunk of Q10B.
|
|
Q11.
|
|
Q11A is the 1st 64-bit chunk of Q11A.
|
|
Q11B is the 2nd 64-bit chunk of Q11B.
|
|
Q12.
|
|
Q12A is the 1st 64-bit chunk of Q12A.
|
|
Q12B is the 2nd 64-bit chunk of Q12B.
|
|
Q13.
|
|
Q13A is the 1st 64-bit chunk of Q13A.
|
|
Q13B is the 2nd 64-bit chunk of Q13B.
|
|
Q14.
|
|
Q14A is the 1st 64-bit chunk of Q14A.
|
|
Q14B is the 2nd 64-bit chunk of Q14B.
|
|
Q15.
|
|
Q15A is the 1st 64-bit chunk of Q15A.
|
|
Q15B is the 2nd 64-bit chunk of Q15B.
|
|
Q1A is the 1st 64-bit chunk of Q1A.
|
|
Q1B is the 2nd 64-bit chunk of Q1B.
|
|
Q2.
|
|
Q2A is the 1st 64-bit chunk of Q2A.
|
|
Q2B is the 2nd 64-bit chunk of Q2B.
|
|
Q3.
|
|
Q3A is the 1st 64-bit chunk of Q3A.
|
|
Q3B is the 2nd 64-bit chunk of Q3B.
|
|
Q4.
|
|
Q4A is the 1st 64-bit chunk of Q4A.
|
|
Q4B is the 2nd 64-bit chunk of Q4B.
|
|
Q5.
|
|
Q5A is the 1st 64-bit chunk of Q5A.
|
|
Q5B is the 2nd 64-bit chunk of Q5B.
|
|
Q6.
|
|
Q6A is the 1st 64-bit chunk of Q6A.
|
|
Q6B is the 2nd 64-bit chunk of Q6B.
|
|
Q7.
|
|
Q7A is the 1st 64-bit chunk of Q7A.
|
|
Q7B is the 2nd 64-bit chunk of Q7B.
|
|
Q8.
|
|
Q8A is the 1st 64-bit chunk of Q8A.
|
|
Q8B is the 2nd 64-bit chunk of Q8B.
|
|
Q9.
|
|
Q9A is the 1st 64-bit chunk of Q9A.
|
|
Q9B is the 2nd 64-bit chunk of Q9B.
|
|
R0.
|
|
R1.
|
|
R10fiq.
|
|
R10usr.
|
|
R11fiq.
|
|
R11usr.
|
|
R12fiq.
|
|
R12usr.
|
|
R2.
|
|
R3.
|
|
R4.
|
|
R5.
|
|
R6.
|
|
R7.
|
|
R8.
|
|
R8fiq.
|
|
R8usr.
|
|
R9fiq.
|
|
R9usr.
|
|
S0.
|
|
S1.
|
|
S10.
|
|
S11.
|
|
S12.
|
|
S13.
|
|
S14.
|
|
S15.
|
|
S16.
|
|
S17.
|
|
S18.
|
|
S19.
|
|
S2.
|
|
S20.
|
|
S21.
|
|
S22.
|
|
S23.
|
|
S24.
|
|
S25.
|
|
S26.
|
|
S27.
|
|
S28.
|
|
S29.
|
|
S3.
|
|
S30.
|
|
S31.
|
|
S4.
|
|
S5.
|
|
S6.
|
|
S7.
|
|
S8.
|
|
S9.
|
|
SB.
|
|
Secure Configuration Register.
|
|
System Control register
|
|
SL.
|
|
SP, the stack pointer.
|
|
Saved Program Status Register.
|
|
SPSRabt.
|
|
SPSRfiq.
|
|
SPSRhyp.
|
|
SPSRirq.
|
|
SPSRmon.
|
|
SPSRsvc.
|
|
SPSRund.
|
|
SPabt.
|
|
SPfiq.
|
|
SPhyp.
|
|
SPirq.
|
|
SPmon.
|
|
SPsvc.
|
|
SPund.
|
|
SPusr.
|
B2R2